Abstract: A method of fabricating an FET or CMOS transistor that includes lightly doped drain ("LDD") regions which minimizes oxide loss while requiring a lesser number of masks. Consequently, manufacturing cost, cycle times and yield loss can be minimized.

Abstract: A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

Abstract: The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

Abstract: The present invention relates to a flash EEPROM cell using polysilicon-to-polysilicon hot electron emission to erase the memory contents of the cell. Exemplary embodiments include a side gate, a control gate, a floating gate and source and drain regions. Appropriate biasing of these gates and source and drain regions controls the electron population of the floating gate. The memory cells may be of either the double polysilicon or triple polysilicon variety. Peripheral transistors are formed from a last formed polysilicon layer to avoid degrading the peripheral transistors.

Abstract: A multilevel antifuse structure characterized by a substrate, a first antifuse structure formed above the substrate, and a second antifuse structure formed above the first antifuse structure. The first antifuse structure preferably includes a first conductive layer, a first antifuse layer disposed over the first conductive layer, a first dielectric layer disposed over the first antifuse layer and provided with a first via hole, and a first conductive via formed within the first via hole. The second antifuse structure preferably includes a second conductive layer, a second antifuse layer disposed over the second conductive layer, a second dielectric layer disposed over the second antifuse layer and provided with a second via hole, and a second conductive via formed within the second via hole. Preferably, the first antifuse layer and the second antifuse layer are patterned into a plurality of antifuse regions which are either vertically aligned or vertically staggered with respect to each other.

Abstract: An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

Abstract: After growth of a thin oxide on a silicon semiconductor body, and formation of a gate thereover, a blanket layer of oxide is deposited over the resulting structure, this oxide layer having, as measured from the surface of the silicon body, relatively thick regions adjacent the sides of the gate and relatively thin regions extending therefrom. Upon implant of ions, the relatively thick regions block ions from passing therethrough into the semiconductor body, while the relatively thin regions allow passage of ions therethrough into the body. After drivein of the ions, the thick layer of oxide is isotopically etched to take a substantially uniform layer therefrom over the entire surface of the thick oxide layer, so that the thick regions thereof are reduced in width. Upon a subsequent ion implant step, the thick regions, now reduced in width from the sides of the gate, block passage of ions therethrough, while the thin regions allow ions therethrough into the silicon body.

Abstract: A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an end-point during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT masking and oxidation steps.

Abstract: A titanium-tungsten barrier layer is sputtered after active areas of a CMOS structure are exposed. An ion implant through the barrier layer and into the active areas disrupts the boundaries between the barrier layer and the underlying active areas. The implant can involve argon or, alternatively, silicon. The resulting structure is annealed. A conductor layer of an aluminum-copper alloy is deposited. An antireflection coating of TiW is deposited. The three-layer structure is then photolithographically patterned to define contacts and local interconnects. The ion implant before anneal results in less contact resistance, which is particularly critical for the barrier layer boundary with positively doped active areas.

Abstract: A conductive via structure establishes an electrical interconnection between two conductive layers in a semiconductor structure by connecting a first conductive layer on a semiconductor substrate to a second conductive layer by means of a conductive via structure extending through a non-conductive layer separating the two conductive layers. The non-conductive layer preferably includes a layer of spin-on-glass (SOG), and is provided with a via aperture therethrough. A conductive spacer, preferably of TiW, is fabricated within the via aperture in abutment with the walls of the via aperture. A second conductive layer is fabricated over the non-conductive layer, the conductive spacer, and within the via aperture, to establish the completed electrical interconnection. The via structure reduces out-gassing and chipping from the SOG layer, yet provides a low electrical resistance path between the two conductive layers.

Abstract: The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.

Abstract: A novel CMOS fabrication process that eliminates several masks of a conventional process by delaying application of a well mask to a semiconductor structure until after formation of isolation regions and gate structures. Providing for three separate implant steps and selectively implanting dopants through an exposure window of the well mask, through gate structures, and through the well mask allows formation of the well region, and source/drain regions in the well region, and in the region covered by the well mask. When LDD implants are desired, removal of a lateral spacer on the gate overlying the well region and subsequent LDD implant through the mask region introduces the LDD implant. Separate masks for source/drain regions and LDD regions are not required. In an alternate embodiment, the LDD implant is introduced prior to formation of lateral spacers on gate structures and application of the well mask, providing the LDD implant in both channels, and eliminating a requirement for lateral spacer removal.

Abstract: The present invention relates to a double poly MOS structure and a method for polysilicon capacitor formation which allows for independent adjustment of an interpoly oxide layer without affecting thickness of the gate oxide layer. In an exemplary embodiment, a first oxide layer is formed above a polysilicon layer. A second oxide layer is subsequently formed on the substrate to establish a gate oxide in an active area of the transistor. As a result, the interpoly oxide layer is formed by a combination of the first and second oxide formations, while the gate oxide layer is formed by only the second oxide formation. Thus, the thickness of the interpoly oxide layer can be adjusted by increasing or decreasing the thickness of the first oxide formation without changing the thickness of the gate oxide layer.

Abstract: A multilevel antifuse structure characterized by a substrate, a first antifuse structure formed above the substrate, and a second antifuse structure formed above the first antifuse structure. The first antifuse structure preferably includes a first conductive layer, a first antifuse layer disposed over the first conductive layer, a first dielectric layer disposed over the first antifuse layer and provided with a first via hole, and a first conductive via formed within the first via hole. The second antifuse structure preferably includes a second conductive layer, a second antifuse layer disposed over the second conductive layer, a second dielectric layer disposed over the second antifuse layer and provided with a second via hole, and a second conductive via formed within the second via hole. Preferably, the first antifuse layer and the second antifuse layer are patterned into a plurality of antifuse regions which are either vertically aligned or vertically staggered with respect to each other.

Abstract: The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.

Abstract: The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.

Abstract: A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer; forming an anti-fuse layer over the base layer; patterning the anti-fuse layer to form an anti-fuse island; forming an insulating layer over the anti-fuse island; forming a via hole through the insulating layer to the anti-fuse island; forming a conductive connection layer over the insulating layer and within the via hole; and patterning the conductive connection layer to form a conductive contact to the anti-fuse island. Preferably, the anti-fuse island comprises amorphous silicon which can optionally be covered with a thin layer of a titanium-tungsten alloy.

Abstract: An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, a conductive protective material, such as titanium tungsten, disposed over the amorphous silicon material, and oxide spacers lining the walls of a recess formed within the protective material. The protective material and the spacers provide tighter programming voltage distributions for the anti-fuse structure and help prevent anti-fuse failure.

Abstract: The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.

Abstract: An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, and oxide spacers lining the walls of a recess formed within the amorphous silicon. The spacers prevent failures of the anti-fuse structures by covering cusps formed in the amorphous silicon material. The method of the present invention forms the above-described anti-fuse structure and further solves the problem of removing unwanted spacer material from areas outside of the anti-fuse structure locations.