Abstract: A bonding pad structure for copper/low-k dielectric material back end of the line (BEOL) processes is disclosed. The bonding pad structure uses a dielectric layer and a conductive pad formed by a gap fill process to protect the underlying bonding pad structure. The conductive pad has a plurality of via plugs in the dielectric layer connecting the underlying bonding pad structure. The bonding pad structure also has a passivation layer having a pad window with a smooth contour to expose the conductive pad.

Abstract: A bonding pad structure. The bonding pad structure includes independently built current conduction structure and mechanical support structure between a bonding pad layer and a substrate. The current conduction structure is constructed using a plurality of serially connected conductive metallic layers each at a different height between the bonding pad layer and the substrate. The conductive metallic layers connect with each other via a plurality of plugs. At least one of the conductive metallic layers connects electrically with a portion of the device in the substrate by a signal conduction line. The mechanical support structure is constructed using a plurality of serially connected supportive metallic layers each at a different height between the bonding pad layer and the substrate. The supportive metallic layers connect with each other via a plurality of plugs.

Abstract: This invention relates to a structure of a dual damascene, in particular to a structure of a dual damascene using in a via. The structure of this dual damascene via comprises of; the first gap, the second gap, the third gap, a barrier layer, the first conductive layer, the second conductive layer, the first dielectric barrier cap, the second dielectric barrier cap, the first low dielectric constant (k) dielectric layer, and the second low dielectric constant dielectric layer. The structure of the present invention can obtain better electromigration (EM) resistance and better via resistance stability by using the third gap to be situated in the first conductive layer.

Abstract: The present invention provides a physical vapor deposition device for forming a metallic layer with a predetermined thickness on a semiconductor wafer. The PVD device comprises a chamber, a wafer chuck installed at the bottom end of the chamber through which the semiconductor wafer is hold horizontally, a metallic ion generator for generating metallic ions, an electric field generator for forming a vertical electric field above the wafer chuck that guides the metallic ions toward the wafer chuck, and a magnetic field generator. The magnetic field generator generates a magnetic field perpendicular to the direction of movement of the metallic ions to create a horizontal moving force on the metallic ions thus causing the metallic ions to deposit on the semiconductor wafer at a slant angle.

Abstract: A method of forming pad openings and fuse openings over a wafer. A wafer having pads and fuses thereon is provided. A passivation layer and a photoresist layer are sequentially formed over the wafer. A photo-exposure and development operation is conducted to remove the photoresist layer above the pads. An etching operation is conducted to remove the passivation layer above the pads as well as the photoresist layer and a portion of the passivation layer above the fuses. Finally, the photoresist layer is removed.

Abstract: A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.

Abstract: A method of forming bonding pad commences by forming a conformal barrier layer on a provided inter-metal dielectric layer. A first metal layer is formed on the barrier layer to partially fill the trench. A thin glue layer is formed on the first metal layer. A second metal layer is formed on the glue layer to fill the trench. The second metal layer, the glue layer, the first metal layer and the barrier layer are partially removed to expose the dielectric layer. A bonding pad structure is thus formed in the trench. The bonding pad structure comprises a first metal pad and a second metal pad.

Abstract: The present invention proposes a method for forming a tungsten film with a good surface property and utilizes a chemical plasma treatment to round the tungsten surface and to improve the leakage issue of tungsten conductive film. A fabrication of a DRAM cell capacitor with tungsten bottom electrode is described for a preferred embodiment. Forming an inter-layer dielectric on a semiconductor substrate, a tungsten layer is formed thereon. A chemical plasma treatment is carried out to round the tungsten surface spires and result in a better surface properties. The tungsten layer is patterned to serve as the bottom electrode, and another dielectric layer is formed to cover the bottom electrode of tungsten. Finally, the top storage electrode is formed to finish the present process.

Abstract: A method for fabricating a metal interconnect structure. A semiconductor substrate comprising a conductive layer therein is provided. A dielectric layer is formed on the semiconductor substrate. A part of the dielectric layer is removed to form a dual damascene opening and a trench therein, wherein the dual damascene opening exposes the conductive layer. The trench is larger than the dual damascene opening. A conformal barrier layer is formed on the dielectric layer. A conformal metal layer is formed on the barrier layer to fill the dual damascene opening and to partially fill the trench. The metal layer positioned in the trench has a thickness equal to the depth of the trench. A conformal cap layer is formed on the metal layer. A CMP process is performed to remove the cap layer, the metal layer and the barrier layer outside the trench and outside the dual damascene opening.

Abstract: A method of fabricating a MOS transistor having an aluminum gate is disclosed. On a MOS transistor having a polysilicon gate, an insulating layer is first formed. The device surface is then polished by CMP to expose the polysilicon gate. Then, an aluminum layer is formed on the substrate and then processed through annealing at more than 500.degree. C. so that a portion of the aluminum layer substitutes the polysilicon gate to form an aluminum gate. After removing the substituted polysilicon and the non-reacted aluminum, the NMOS transistor with an aluminum gate is completed.

Abstract: A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.

Abstract: A method is described for manufacturing a multilevel metal interconnects. The method comprises the steps of providing a substrate and then forming a wire on the substrate. A dielectric layer is formed on the substrate and the wire and a protective layer is formed on the dielectric layer. An opening is formed by patterning the protective layer and the dielectric layer and a barrier layer is formed on the protective layer and in the opening. A copper layer is formed on the barrier layer and fills the opening. A portion of the copper layer and the barrier layer are removed by chemical-mechanical polishing.

Abstract: A deposition method for improving the step coverage of contact holes is disclosed. The method includes initially placing a semiconductor substrate on a chuck of a chamber, wherein the substrate has some contact holes. The chuck is firstly adjusted and conductive material is firstly deposited onto the substrate, wherein the direction of the first deposition is about vertical to the surface of the substrate, and therefore the bottom of the contact holes is then substantially deposited with the conductive material. Next, the chuck is secondly adjusted so that it has a tilt angle between the direction of the second deposition and rotation axis of the chuck. Finally, the chuck is continuously rotated and the conductive material is secondly deposited onto the substrate, and therefore the sidewall of the contact holes is then substantially deposited with the conductive material.

Abstract: A self-aligned via process to prevent the via poisoning includes forming a hydrogen silsesquioxane layer on the substrate and over a pre-formed metal layer, forming an etching stop layer on the hydrogen silsesquioxane layer, forming an oxide layer on the etching stop layer, and then proceeding with a two-step etching process to form a via. The two-step etching process first patterns the oxide layer using a patterned photoresist layer as a mask, and then patterns the etching stop layer together with the hydrogen silsesquioxane layer using the patterned oxide layer as a mask. Because the etching stop layer prevents the hydrogen silsesquioxane layer from reacting with the oxygen plasma during the photoresist layer removal process, via poisoning is eliminated.

Abstract: A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias.