Patents by Inventor Kunihiro Katayama
Kunihiro Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240134127Abstract: An object of the present disclosure is to provide a simple, compact optical switch with low power consumption.Type: ApplicationFiled: February 3, 2021Publication date: April 25, 2024Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Chisato FUKAI, Kunihiro TOGE, Yoshiteru ABE, Kazunori KATAYAMA
-
Publication number: 20240094477Abstract: An objective of the present disclosure is to provide an optical coupler and an optical switch capable of achieving stable optical characteristics with low power consumption and more economical efficiency with respect to external factors.Type: ApplicationFiled: January 27, 2021Publication date: March 21, 2024Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Chisato FUKAI, Yoshiteru ABE, Kunihiro TOGE, Kazunori KATAYAMA
-
Patent number: 9007830Abstract: A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein, and a storage region storing registered address values of faulty regions of the main storage medium containing the faulty memory cells. Data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit. An administrative information region is provided in each block. The control unit carries out access requests of the main storage medium and the administration of faulty regions and the number of occurrences of reloading of respective memory cells of the main storage medium.Type: GrantFiled: August 6, 2013Date of Patent: April 14, 2015Assignee: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
-
Patent number: 8897736Abstract: A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Specifically, the following is implemented: when there is the supply of required power from the battery, it is made possible to carry out high-performance, multifunctional authentication and settlement processing making good use of high-speed processing, mass storage, and the like which are the advantages of the security controller essentially driven by battery; and in an anomalous instance in which the battery remaining capacity is lost, it is made possible to carry out minimal authentication and settlement processing.Type: GrantFiled: June 19, 2013Date of Patent: November 25, 2014Assignee: Renesas Electronics CorporationInventors: Shigemasa Shiota, Kunihiro Katayama, Shinichi Fukasawa, Takeo Kon, Seiji Kobayashi
-
Publication number: 20140185380Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: ApplicationFiled: August 6, 2013Publication date: July 3, 2014Applicant: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi INOUE, Shigemasa SHIOTA, Masashi NAITO
-
Publication number: 20140011451Abstract: A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Specifically, the following is implemented: when there is the supply of required power from the battery, it is made possible to carry out high-performance, multifunctional authentication and settlement processing making good use of high-speed processing, mass storage, and the like which are the advantages of the security controller essentially driven by battery; and in an anomalous instance in which the battery remaining capacity is lost, it is made possible to carry out minimal authentication and settlement processing.Type: ApplicationFiled: June 19, 2013Publication date: January 9, 2014Applicant: Renesas Electronics CorporationInventors: Shigemasa Shiota, Kunihiro Katayama, Shinichi Fukasawa, Takeo Kon, Seiji Kobayashi
-
Patent number: 8503235Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: GrantFiled: November 17, 2011Date of Patent: August 6, 2013Assignee: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
-
Patent number: 8478224Abstract: A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Thus the noncontact authentication and settlement functions can be used even after the battery remaining capacity is lost by use of a communication function for the principal purpose.Type: GrantFiled: July 18, 2010Date of Patent: July 2, 2013Assignee: Renesas Electronics CorporationInventors: Shigemasa Shiota, Kunihiro Katayama, Shinichi Fukasawa, Takeo Kon, Seiji Kobayashi
-
Patent number: 8331153Abstract: In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range.Type: GrantFiled: February 1, 2012Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
-
Publication number: 20120213002Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: ApplicationFiled: November 17, 2011Publication date: August 23, 2012Inventors: Kunihiro KATAYAMA, Takayuki TAMURA, Satoshi WATATANI, Kiyoshi INOUE, Shigemasa SHIOTA, Masashi NAITO
-
Publication number: 20120127792Abstract: In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Inventors: Kunihiro KATAYAMA, Takayuki Tamura, Kiyoshi Inoue
-
Patent number: 8134869Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: GrantFiled: August 10, 2011Date of Patent: March 13, 2012Assignee: Renesas Electronics CorporationInventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
-
Publication number: 20120011307Abstract: A semiconductor storage apparatus is coupled with a system bus to receive a write request accompanied with first and second blocks of data, which are stored in nonvolatile semiconductor memories. A control device sends a first erase command to one of the nonvolatile memories to initiate a first internal erase operation of data within the nonvolatile memories. After the first erase command has been sent, the control device sends a second erase command to another one of the nonvolatile memories, to initiate a second internal erase operation of data within the other nonvolatile memory.Type: ApplicationFiled: August 16, 2011Publication date: January 12, 2012Inventors: Kenichi Kaki, Kunihiro Katayama, Takashi Tsunehiro
-
Publication number: 20110292727Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: ApplicationFiled: August 10, 2011Publication date: December 1, 2011Inventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
-
Patent number: 8064257Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: GrantFiled: November 10, 2009Date of Patent: November 22, 2011Assignee: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
-
Patent number: 8051331Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: GrantFiled: March 26, 2009Date of Patent: November 1, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Hidefumi Oodate, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
-
Patent number: 8031536Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.Type: GrantFiled: March 29, 2010Date of Patent: October 4, 2011Assignee: S4, Inc.Inventors: Hajime Yamagami, Kouichi Terada, Yoshihiro Hayashi, Takashi Tsunehiro, Kunihiro Katayama, Kenichi Kaki, Takeshi Furuno
-
Patent number: 8023325Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: GrantFiled: February 1, 2011Date of Patent: September 20, 2011Assignee: Renesas Technology CorporationInventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
-
Patent number: 8001319Abstract: A semiconductor storage apparatus is coupled with a system bus to receive a write request accompanied with first and second blocks of data, which are stored in nonvolatile semiconductor memories. A control device sends a first erase command to one of the nonvolatile memories to initiate a first internal erase operation of data within the nonvolatile memories. After the first erase command has been sent, the control device sends a second erase command to another one of the nonvolatile memories, to initiate a second internal erase operation of data within the other nonvolatile memory.Type: GrantFiled: May 15, 2009Date of Patent: August 16, 2011Assignee: Solid State Storage Solutions, Inc.Inventors: Kenichi Kaki, Kunihiro Katayama, Takashi Tsunehiro
-
Patent number: RE45857Abstract: A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.Type: GrantFiled: May 18, 2012Date of Patent: January 19, 2016Assignee: Solid State Storage Solutions, IncInventors: Takayuki Tamura, Shigemasa Shiota, Kunihiro Katayama, Masashi Naito