Patents by Inventor Kunihiro Katayama
Kunihiro Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7996911Abstract: In order to protect the user security data, provided is a memory card capable of preventing the data leakage to a third party not having the access authority by imposing the limitation on the number of password authentications and automatically erasing the data. In a system comprised of a multimedia card and a host machine electrically connected to the multimedia card and controlling the operations of the multimedia card, a retry counter for storing the number of password authentication failures is provided and the upper limit of the number of failures is registered in a register. When passwords are repeatedly entered once, twice, . . . and n times and the retry counter which counts the entries reaches the upper limit of the number of failures, the data is automatically erased so as not to leave the data in the flash memory.Type: GrantFiled: July 29, 2008Date of Patent: August 9, 2011Assignee: Renesas Electronics CorporationInventors: Satoshi Yoshida, Kunihiro Katayama, Akira Kanehira, Masaharu Ukeda
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Publication number: 20110122701Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: ApplicationFiled: February 1, 2011Publication date: May 26, 2011Inventors: Kunihiro KATAYAMA, Takayuki Tamura, Kiyoshi Inoue
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Patent number: 7908424Abstract: A controller 3 of a memory card is a provided with a command decoding circuit 6 for decoding commands issued by a host HT, a command enable register 8 in which the validity or invalidity of the received command, and a command detection signal generating circuit 7 for detecting a valid command on the basis of the result of decoding by the command decoding circuit 6 and a value set by the command enable register 8. If the command enable register 8 receives a validly set command, the command detection signal generating circuit 7 will supply a detection signal to a control unit 4 to execute processing prescribed for each command. the command enable register 8 receives an invalidly set command, no detection signal will be supplied, and the command will be ignored.Type: GrantFiled: May 29, 2007Date of Patent: March 15, 2011Assignee: Renesas Electronics CorporationInventors: Atsushi Shikata, Kunihiro Katayama, Masato Matsumoto, Kazuto Izawa, Motoki Kanamori
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Publication number: 20110034124Abstract: A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Thus the noncontact authentication and settlement functions can be used even after the battery remaining capacity is lost by use of a communication function for the principal purpose.Type: ApplicationFiled: July 18, 2010Publication date: February 10, 2011Inventors: Shigemasa SHIOTA, Kunihiro Katayama, Shinichi Fukasawa, Takeo Kon, Seiji Kobayashi
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Patent number: 7881111Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: GrantFiled: July 16, 2009Date of Patent: February 1, 2011Assignee: Renesas Technology CorporationInventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
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Publication number: 20100191902Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.Type: ApplicationFiled: March 29, 2010Publication date: July 29, 2010Inventors: Hajime Yamagami, Kouichi Terada, Yoshihiro Hayashi, Takashi Tsunehiro, Kunihiro Katayama, Kenichi Kaki, Takeshi Furuno
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Publication number: 20100177579Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: ApplicationFiled: November 10, 2009Publication date: July 15, 2010Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Patent number: 7721165Abstract: A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.Type: GrantFiled: November 15, 2006Date of Patent: May 18, 2010Assignee: Solid State Storage Solutions, Inc.Inventors: Takayuki Tamura, Shigemasa Shiota, Kunihiro Katayama, Masashi Naito
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Patent number: 7715243Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.Type: GrantFiled: December 17, 2007Date of Patent: May 11, 2010Assignee: S4, Inc.Inventors: Hajime Yamagami, Kouichi Terada, Yoshihiro Hayashi, Takashi Tsunehiro, Kunihiro Katayama, Kenichi Kaki, Takeshi Furuno
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Patent number: 7694067Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.Type: GrantFiled: January 16, 2008Date of Patent: April 6, 2010Assignee: Renesas Technology Corp.Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
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Publication number: 20100014351Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: ApplicationFiled: July 16, 2009Publication date: January 21, 2010Inventors: Kunihiro KATAYAMA, Takayuki Tamura, Kiyoshi Inoue
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Patent number: 7650503Abstract: A memory card has: a flash memory chip for storing digital certificates and a seed of random numbers; a controller chip which can execute a managing process for managing the digital certificates and a random number generating process for generating the pseudo random numbers by using the seed of random numbers; and an IC card chip which can execute an authenticating process for authenticating personal identification information (PIN) inputted from a host apparatus and an encrypting process for encrypting the seed of random numbers. Thus, a processing time of security processes is reduced while assuring safety of the security processes.Type: GrantFiled: November 13, 2007Date of Patent: January 19, 2010Assignee: Renesas Technology Corp.Inventors: Nagamasa Mizushima, Motoyasu Tsunoda, Kunihiro Katayama
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Patent number: 7616485Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: GrantFiled: October 31, 2007Date of Patent: November 10, 2009Assignee: Solid State Storage Solutions LLCInventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Patent number: 7610419Abstract: An image data serial signal output from the parallel-serial converting circuit 21 is converted into a differential amplitude signal by the LVDS transmitter 22 in such a manner that the amplitude of the differential voltage of the image data parallel signal varies depending on the value of the synchronization code serial signal. Accordingly, the signal values of the synchronization code serial signal and the image data serial signal are simultaneously transmitted. On the reception side, the differential amplitude signal in which the amplitude of the differential voltage of the image data serial signal varies depending on the value of the synchronization code serial signal is received by the LVDS receiver 31. The signal values of the synchronization code serial signal and the image data serial signal are separated and output based on a predetermined comparison processing.Type: GrantFiled: July 5, 2005Date of Patent: October 27, 2009Assignee: Sharp Kabushiki KaishaInventors: Takumi Hashimoto, Kunihiro Katayama, Yoshiaki Nakade, Yasuki Kawasaka, Masayuki Shinagawa
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Publication number: 20090228643Abstract: A semiconductor storage apparatus is coupled with a system bus to receive a write request accompanied with first and second blocks of data, which are stored in nonvolatile semiconductor memories. A control device sends a first erase command to one of the nonvolatile memories to initiate a first internal erase operation of data within the nonvolatile memories. After the first erase command has been sent, the control device sends a second erase command to another one of the nonvolatile memories, to initiate a second internal erase operation of data within the other nonvolatile memory.Type: ApplicationFiled: May 15, 2009Publication date: September 10, 2009Inventors: Kenichi Kaki, Kunihiro Katayama, Takashi Tsunehiro
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Patent number: 7570515Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: GrantFiled: October 10, 2007Date of Patent: August 4, 2009Assignee: Renesas Technology CorporationInventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
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Publication number: 20090187703Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: ApplicationFiled: March 26, 2009Publication date: July 23, 2009Inventors: HIDEFUMI OODATE, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
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Patent number: 7558110Abstract: In a SIM card having a flash memory chip, a memory controller chip, and contact/contactless card interfaces, the memory controller chip has a function of executing user authentication of a host equipment, executes processing of data transmitted through the contactless IC card interface (executing reading or writing of data to the flash memory chip) using power supplied from the host equipment to the contact IC card interface, and executes initialization of the flash memory chip between activation of the host equipment and completion of user authentication instructed by the host equipment.Type: GrantFiled: April 27, 2007Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Nagamasa Mizushima, Kunihiro Katayama, Masaharu Ukeda, Yoshinori Mochizuki
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Patent number: 7549086Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: GrantFiled: October 23, 2007Date of Patent: June 16, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Sytems Co., Ltd.Inventors: Hidefumi Oodate, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
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Publication number: 20090013125Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.Type: ApplicationFiled: January 16, 2008Publication date: January 8, 2009Inventors: Nagamasa MIZUSHIMA, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano