Patents by Inventor Kunihiro Katayama
Kunihiro Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080301817Abstract: In order to protect the user security data, provided is a memory card capable of preventing the data leakage to a third party not having the access authority by imposing the limitation on the number of password authentications and automatically erasing the data. In a system comprised of a multimedia card and a host machine electrically connected to the multimedia card and controlling the operations of the multimedia card, a retry counter for storing the number of password authentication failures is provided and the upper limit of the number of failures is registered in a register. When passwords are repeatedly entered once, twice, . . . and n times and the retry counter which counts the entries reaches the upper limit of the number of failures, the data is automatically erased so as not to leave the data in the flash memory.Type: ApplicationFiled: July 29, 2008Publication date: December 4, 2008Inventors: Satoshi Yoshida, Kunihiro Katayama, Akira Kanehire, Masaharu Ukeda
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Patent number: 7447072Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.Type: GrantFiled: November 15, 2006Date of Patent: November 4, 2008Assignee: Solid State Storage Solutions LLCInventors: Hajime Yamagami, Kouichi Terada, Yoshihiro Hayashi, Takashi Tsunehiro, Kunihiro Katayama, Kenichi Kaki, Takeshi Furuno
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Patent number: 7418602Abstract: In order to protect the user security data, provided is a memory card capable of preventing the data leakage to a third party not having the access authority by imposing the limitation on the number of password authentications and automatically erasing the data. In a system comprised of a multimedia card and a host machine electrically connected to the multimedia card and controlling the operations of the multimedia card, a retry counter for storing the number of password authentication failures is provided and the upper limit of the number of failures is registered in a register. When passwords are repeatedly entered once, twice, . . . and n times and the retry counter which counts the entries reaches the upper limit of the number of failures, the data is automatically erased so as not to leave the data in the flash memory.Type: GrantFiled: June 17, 2004Date of Patent: August 26, 2008Assignee: Renesas Technology Corp.Inventors: Satoshi Yoshida, Kunihiro Katayama, Akira Kanehira, Masaharu Ukeda
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Patent number: 7415729Abstract: A storage device allows expanding user utilizable applications by storing information permitted to be read according to a certificate and information permitted to be read according to information determined by a user. An information distributor receives a certificate from the storage device and after verifying the certificate, transmits data of a license and access control conditions to the storage device. After receiving data of a certificate from an information browser, verifying the certificate and imposing a limit on access based upon one of access control conditions, the storage device transmits data of the license and the other to the information browser. The information browser permits utilization of the license under the limitation defined by the access control condition. The certificate includes either or both of a certificate approved by a certificate authority and a PIN (personal identifying number) determined by the user.Type: GrantFiled: June 18, 2003Date of Patent: August 19, 2008Assignee: Hitachi, Ltd.Inventors: Masaharu Ukeda, Motoyasu Tsunoda, Nagamasa Mizushima, Kunihiro Katayama
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Patent number: 7403436Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.Type: GrantFiled: June 16, 2006Date of Patent: July 22, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Motoki Kanamori, Kunihiro Katayama, Atsushi Shiraishi, Shigeo Kurakata, Atsushi Shikata
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Patent number: 7379379Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.Type: GrantFiled: November 15, 2006Date of Patent: May 27, 2008Assignee: Solid State Storage Solutions LLCInventors: Hajime Yamagami, Kouichi Terada, Yoshihiro Hayashi, Takashi Tsunehiro, Kunihiro Katayama, Kenichi Kaki, Takeshi Furuno
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Publication number: 20080106939Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.Type: ApplicationFiled: December 17, 2007Publication date: May 8, 2008Inventors: Hajim Yamagami, Kouichi Terada, Yoshihiro Hayashi, Takashi Tsunehiro, Kunihiro Katayama, Kenichi Kaki, Takeshi Furuno
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Patent number: 7370168Abstract: The invention intends to provide a memory card conforming to an HS-MMC mode in a standard of a multimedia card, while securing compatibility of both standards of the multimedia card and an SD card. In a normal MMC mode, the data is outputted at a fall edge of a clock signal. A frequency of the clock signal is about 20 MHz. When the data is outputted at the fall edge of the clock signal, data output is in time for a next clock signal. When a parameter ‘1’ is set to a timing register provided in a host interface, the memory card is transitioned into the HS-MMC mode. In the HS-MMC mode, a clock signal frequency is increased to about 52 MHz. Here, the data is outputted at the rise edge of the clock signal, whereby the data output is brought in time for the rise edge of the next clock signal.Type: GrantFiled: March 30, 2004Date of Patent: May 6, 2008Assignee: Renesas Technology Corp.Inventors: Motoki Kanamori, Kunihiro Katayama, Yasuhiro Nakamura, Satoshi Yoshida, Shinsuke Asari
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Publication number: 20080091900Abstract: The disclosed invention effectively prevents fraudulent access to data whose usage is restricted to a time limit, such access attempted by manipulating the clock internal to a playback device and a terminal device. A nonvolatile memory device of the invention comprises a control circuit and a nonvolatile memory circuit which includes a storage region for restriction information to restrict access to contents information provided by web-based rental service. The restriction information includes access time limit information and access time stamp information. The control circuit performs an access decision action which comprises deciding whether access to the contents information is enabled or disabled, based on real time information which is supplied externally and the restriction information, and updating the access time stamp information to the realtime information.Type: ApplicationFiled: November 30, 2007Publication date: April 17, 2008Inventors: Tsutomu IMAI, Akira Kanehira, Kunihiro Katayama
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Patent number: 7356659Abstract: There is provided semiconductor memory capable of reconfiguring an area to be given an authentication key and access limitation, and there is implemented an information distribution system having an advanced security function using the semiconductor memory. Part of a storage area in the semiconductor memory stores information about the area to be given the authentication key and the access limitation. Alternatively, the authentication key is stored in units of data to be authenticated for limiting an access to stored information. Information is protected doubly by storing encrypted information in the area provided with the access limitation according to the above-mentioned method.Type: GrantFiled: December 8, 2005Date of Patent: April 8, 2008Assignee: Renesas Technology Corp.Inventors: Naoki Kobayashi, Yuji Satou, Hideaki Kurata, Kunihiro Katayama, Takayuki Kawahara
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Publication number: 20080082825Abstract: A memory card has: a flash memory chip for storing digital certificates and a seed of random numbers; a controller chip which can execute a managing process for managing the digital certificates and a random number generating process for generating the pseudo random numbers by using the seed of random numbers; and an IC card chip which can execute an authenticating process for authenticating personal identification information (PIN) inputted from a host apparatus and an encrypting process for encrypting the seed of random numbers. Thus, a processing time of security processes is reduced while assuring safety of the security processes.Type: ApplicationFiled: November 13, 2007Publication date: April 3, 2008Inventors: Nagamasa Mizushima, Motoyasu Tsunoda, Kunihiro katayama
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Patent number: 7350023Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip, wherein, the flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.Type: GrantFiled: December 11, 2006Date of Patent: March 25, 2008Assignee: Renesas Technology Corp.Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
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Patent number: 7343445Abstract: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition.Type: GrantFiled: October 3, 2006Date of Patent: March 11, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kunihiro Katayama, Motoki Kanamori, Atsushi Shikata, Hidefumi Oodate, Atsushi Shiraishi
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Publication number: 20080055986Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: ApplicationFiled: October 31, 2007Publication date: March 6, 2008Inventors: Kunihiro KATAYAMA, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Publication number: 20080059852Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: ApplicationFiled: October 23, 2007Publication date: March 6, 2008Inventors: Hidefumi Oodate, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
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Publication number: 20080037322Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: ApplicationFiled: October 10, 2007Publication date: February 14, 2008Inventors: Kunihiro KATAYAMA, Takayuki Tamura, Kiyoshi Inoue
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Patent number: 7327624Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.Type: GrantFiled: November 15, 2006Date of Patent: February 5, 2008Assignee: Solid State Storage Solutions, LLCInventors: Hajime Yamagami, Kouichi Terada, Yoshihiro Hayashi, Takashi Tsunehiro, Kunihiro Katayama, Kenichi Kaki, Takeshi Furuno
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Patent number: 7305589Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: GrantFiled: May 8, 2002Date of Patent: December 4, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hidefumi Oodate, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
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Patent number: 7303136Abstract: A storage device to store data includes an external interface, a controller, a nonvolatile memory, and an IC card. In response to a first indication from the external device, the controller receives a program to be executed in the IC card from the nonvolatile memory or the external device and writes the program in the IC card. In response to a second indication from the external device, the controller deletes the program written in the IC card.Type: GrantFiled: March 3, 2004Date of Patent: December 4, 2007Assignee: Renesas Technology Corp.Inventors: Motoyasu Tsunoda, Nagamasa Mizushima, Kunihiro Katayama
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Patent number: 7295467Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: GrantFiled: August 19, 2005Date of Patent: November 13, 2007Assignee: Renesas Technology Corp.Inventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue