Abstract: A method including forming a first insulating film over a first fin structure. The method further includes removing the first insulating film to expose a portion of the first fin structure. The method further includes forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.

Abstract: One of gamma ray lithography systems includes a gamma ray generator and a wafer stage. The gamma ray generator is configured to generate a substantially uniform gamma ray. The gamma ray generator includes a plurality of gamma ray sources and a rotational carrier. The rotational carrier is configured to hold the gamma ray sources and rotate along a rotational axis. The wafer stage is disposed below the gamma ray generator and configured to secure a wafer.

Abstract: A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.

Abstract: One of gamma ray lithography systems includes a gamma ray generator and a wafer stage. The gamma ray generator is configured to generate a substantially uniform gamma ray. The gamma ray generator includes a plurality of gamma ray sources and a rotational carrier. The rotational carrier is configured to hold the gamma ray sources and rotate along a rotational axis. The wafer stage is disposed below the gamma ray generator and configured to secure a wafer.

Abstract: A method of patterning a material layer includes the following steps. A first material layer is formed over a substrate, and the first material layer includes a first metal compound. Through a first photomask, portions of the first material layer is exposed with a gamma ray, wherein a first metal ion of the first metal compound in the portions of the first material layer is chemically reduced to a first metal grain. Other portions of the first material layer are removed to form a plurality of first hard mask patterns including the first metal grain.

Abstract: A method of manufacturing a photomask includes depositing a first absorbing layer over a substrate, patterning the first absorbing layer using a photoresist, and depositing a conformal second absorbing layer along surfaces of the first absorbing layer.

Abstract: An integrated system operation method is disclosed that includes the following steps: the film of a substrate is measured by a metrology apparatus to obtain a film information. The substrate is moved from the metrology apparatus to a process apparatus adjacent to the transfer apparatus. The film information is sent to the process apparatus. A film treatment is applied to the substrate in accordance with the film information.

Abstract: A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma to form the conductive powder. The method further includes filtering the conductive powder based on particle size. The method further includes dispersing a portion of the conductive powder having a particle size below a threshold value in a fluid.

Abstract: A transistor includes a silicon germanium layer, a gate stack, and source and drain features. The silicon germanium layer has a channel region. The silicon germanium layer has a first silicon-to-germanium ratio. The gate stack is disposed over the channel region of the silicon germanium layer and includes a silicon germanium oxide layer over and in contact with the channel region of the silicon germanium layer, a high-? dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-? dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio, and the second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio.

Abstract: A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma. Reducing the conductive powder precursor gas forms the conductive powder. The method further includes filtering the conductive powder based on particle size. The method further includes dispersing a portion of the conductive powder having a particle size below a threshold value in a fluid.

Abstract: A method of evaluating characteristics of a work piece includes forming a photosensitive layer on the work piece. Then an ion implantation is performed on the work piece. The work piece is radiated, and an optical intensity of the photosensitive material on the work piece is calculated. The ion implantation pattern is evaluated according to the optical intensity. A chemical structure of the photosensitive material is changed upon the ion implantation. The work piece is recovered by reversing the chemical structure of the photosensitive material or removing the ion interrupted photosensitive material by chemicals.

Abstract: A transistor includes a channel region, a gate stack, and source and drain structures. The channel region comprises silicon germanium and has a first silicon-to-germanium ratio. The gate stack is over the channel region and comprises a silicon germanium oxide layer over the channel region, a high-? dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-? dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio. The second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio. The channel region is between the source and drain structures.

Abstract: A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.

Abstract: A photomask includes a patterned photomask plate and a supporting member. The patterned photomask plate has a pattern region and a peripheral region surrounding the pattern region. The patterned photomask plate includes a plurality of openings in the pattern region. The supporting member directly abuts the patterned photomask plate and is in a peripheral region of the patterned photomask plate. The supporting member is formed from a different material than the patterned photomask plate.

Abstract: A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature.

Abstract: A method including forming a first insulating film over a first fin structure. The method further includes removing the first insulating film to expose a portion of the first fin structure. The method further includes forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.

Abstract: A semiconductor processing station including a platform, a load port, and a carrier transport track is provided. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transport track has a bottom side configured to open the load chamber.

Abstract: A method of aligning a substrate contact material to a substrate material includes determining a hardness of a substrate material. The method further includes matching a hardness of a substrate contact material to the hardness of the substrate material. The method further includes adding the substrate contact material to a plurality of contact structures of a substrate handling device, wherein the substrate handling device comprises an edge and a planar surface, a first contact structure of the plurality of contact structures extends from the edge, and a second contact structure of the plurality of contact structures extends from the planar surface.

Abstract: A method for forming a photomask includes the following steps. A substrate is provided, which has a pattern region and a peripheral region surrounding the pattern region. A first etching operation is performed on a first surface of the substrate to remove first portions of the substrate in the pattern region, so as to form recesses in the pattern region of the substrate. A blasting operation is performed on the first surface of the substrate. A BARC layer is formed filling the recesses and over the first surface of the substrate. A second etching operation is performed on a second surface of the substrate opposite to the first surface until portions of the BARC layer in the recesses are exposed. The BARC layer is removed after the second etching operation, so as to form openings in the substrate in the pattern region.

Abstract: A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.