Abstract: The present invention relates to a lithium-carbon composite having cavities formed therein and a method of manufacturing the same, the method including adding and mixing an organic solvent having an aromatic ring with a lithium precursor, arranging a pair of metal wires in the organic solvent, forming a lithium-carbon composite in which a carbon body is doped with lithium through plasma discharge in a solution, and annealing the lithium-carbon composite in order to remove hydrogen from the lithium-carbon composite and form cavities in the lithium-carbon composite. Accordingly, a lithium-carbon composite can be simply synthesized using plasma discharge in a solution, and the synthesized lithium-carbon composite can be annealed to thus form cavities therein, thereby increasing the lithium charge and discharge performance of a lithium secondary battery using the lithium-carbon composite.

Abstract: Disclosed herein are a calcium salts-supported metal catalyst, a method for preparing the same, and a method for the hydrodeoxygenation reaction of oxygenates using the same. The catalyst, in which a metal catalyst is supported on a carrier of a calcium salt, for example, calcium carbonate, has the effect of increasing the efficiency of hydrodeoxygenation reaction of oxygenates.

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

Abstract: Disclosed are a method for producing lactic acid from wastes containing cellulose and/or hemicellulose and a catalyst for thermochemical conversion reaction of wastes containing cellulose and/or hemicellulose. The method includes a step of adding a metal catalyst to wastes containing cellulose and/or hemicellulose and performing thermochemical conversion reaction. The method provides an effect of producing lactic acid from discarded wastes, e.g., waste paper such as waste corrugated paperboards, waste paper boxes, waste newspapers, etc.

Abstract: A method for retrieval of lost radial velocity in weather radar includes expanding a radial velocity area to non-meteorological echoes including sea clutter and chaff echo using raw radar data for use of a wind field calculation area, correcting radial velocity by replacing the radial velocity determined as noise using a median sign comparison method with a median calculated within a window to which the radial velocity belongs, distinguishing a lost radial velocity area by comparing the corrected radial velocity with radar reflectivity data, and retrieving lost radial velocity using a Velocity Azimuth Display (VAD) fit function representing radial velocity of particles observed along a radar radiation source at a certain elevation in the lost radial velocity area as a function of an azimuth angle. Accordingly, it is possible to improve the quality of calculated wind field using the improved radar radial velocity, and provide more accurate dynamic structure information of the precipitation system.

Abstract: A temperature sensing device including a first temperature sensor having a first resistor and a first capacitor and generating a first voltage applied to at least one of the first resistor or the first capacitor based on a first clock signal and a second clock signal generated by delaying the first clock signal, a second temperature sensor having a second resistor and a second capacitor and generating a second voltage applied to at least one of the second resistor or the second capacitor based on the first and second clock signals, a controller generating code data based on the first voltage and the second voltage and generating a control signal based on the code data, and a delay locked loop circuit delaying the first clock signal based on the control signal to generate the second clock signal may be provided.

Abstract: A precipitation nowcasting method using dynamic motion vectors includes calculating a multiscale motion vector of a radar precipitation motion vector and a numerical model precipitation motion vector by changing spatial scale of cross correlation analysis for reach of a preset time interval from precipitation data obtained through a dual polarization radar, calculating a dynamic motion vector by merging the radar precipitation motion vector and the numerical model precipitation motion vector, generating a precipitation development and dissipation map through precipitation tracking and matching using the dynamic motion vector, and outputting a precipitation forecast field for each forecast time by applying the dynamic motion vector and the precipitation development and dissipation map to Lagrangian backward extrapolation. Accordingly, it is possible to achieve realistic precipitation forecast field simulation.

Abstract: A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers; memory openings extending through the alternating stack, memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, a source layer contacting the vertical semiconductor channels, a backside isolation dielectric layer contacting a backside surface of the source layer, and a source power supply mesh including a planar portion of a source-side electrically conductive layer that is located on a backside of the backside isolation dielectric layer and electrically connected to the source layer by conductive material portions that extend through the backside isolation dielectric layer.

Abstract: Through-substrate via structures are formed in a semiconductor substrate of a first semiconductor die. Semiconductor devices, dielectric material layers, and metal interconnect structures are formed over a front surface of the semiconductor substrate. A backside dielectric layer is formed on a backside surface. Integrated line and pad structures are formed over the backside dielectric layer on a respective through-substrate via structure. Each of the integrated line and pad structures includes a respective pad portion and respective line portion that extends from a center region of the backside surface to toward a periphery of the backside surface. A bonded assembly including the first semiconductor die and a second semiconductor die can be formed. Bonding pads can be provided in a center region of the interface between the semiconductor dies to facilitate power and signal distribution in the second semiconductor die with less electrical wiring.

Abstract: According to the embodiments disclosed herein, in a press-fitting test for measuring physical properties of a test object by pressing an indenter against the test object and measuring the load and displacement, the measured displacement value is corrected in real time in consideration of the amount of deformation according to the load of the load cell, and thus an accurate load-displacement curve can be derived, even when the amount of deformation of the load cell is included in a measured value of a displacement sensor.

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

Abstract: A reference voltage generating circuit includes: an operational amplifier including a first input terminal connected to a first node and a second input terminal connected to a second node; a first transistor connected between a ground terminal and the first node, wherein a first current flows in the first transistor; a second transistor connected to the ground terminal; and a first variable resistor connected between the second transistor and the second node, wherein the first variable resistor has a first resistance value for adjusting the first current, based on a change in a current characteristic of the first transistor caused by a variation in a process of forming the first transistor. The reference voltage generating circuit provides a reference voltage, based on a voltage of the first node and a voltage across the first variable resistor.

Abstract: A precipitation nowcasting method using dynamic motion vectors includes calculating a multiscale motion vector of a radar precipitation motion vector and a numerical model precipitation motion vector by changing spatial scale of cross correlation analysis for reach of a preset time interval from precipitation data obtained through a dual polarization radar, calculating a dynamic motion vector by merging the radar precipitation motion vector and the numerical model precipitation motion vector, generating a precipitation development and dissipation map through precipitation tracking and matching using the dynamic motion vector, and outputting a precipitation forecast field for each forecast time by applying the dynamic motion vector and the precipitation development and dissipation map to Lagrangian backward extrapolation. Accordingly, it is possible to achieve realistic precipitation forecast field simulation.

Abstract: A method for retrieval of lost radial velocity in weather radar includes expanding a radial velocity area to non-meteorological echoes including sea clutter and chaff echo using raw radar data for use of a wind field calculation area, correcting radial velocity by replacing the radial velocity determined as noise using a median sign comparison method with a median calculated within a window to which the radial velocity belongs, distinguishing a lost radial velocity area by comparing the corrected radial velocity with radar reflectivity data, and retrieving lost radial velocity using a Velocity Azimuth Display (VAD) fit function representing radial velocity of particles observed along a radar radiation source at a certain elevation in the lost radial velocity area as a function of an azimuth angle. Accordingly, it is possible to improve the quality of calculated wind field using the improved radar radial velocity, and provide more accurate dynamic structure information of the precipitation system.

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

Abstract: A method for calculating the uncertainty of a data-based model, includes: a memory data generation step (S10); a measurement data receiving step (S20); a Euclidean distance calculation step (S30); a kernel function calculation step (S40); a weighted area-specific effective number calculation step (S50) of calculating a weighted area-specific effective number (Nn); a weighted value setting step (S60) of setting a weighted area-specific weighted value (Wn); a total effective number calculation step (S70) of calculating a total effective number (Nt) according to a weighted value; a prediction data calculation step (S80) of calculating prediction data (Xq) about measurement data (Q); a weighted standard deviation calculation step (S90) of calculating a weighted standard deviation (Sw); and an uncertainty calculation step (S100) of calculating uncertainty (U) so as to determine the reliability of prediction data by means of the calculated uncertainty (U).