Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.

Abstract: In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body.

Abstract: In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body.

Abstract: The present invention relates to a lithium-carbon composite having cavities formed therein and a method of manufacturing the same, the method including adding and mixing an organic solvent having an aromatic ring with a lithium precursor, arranging a pair of metal wires in the organic solvent, forming a lithium-carbon composite in which a carbon body is doped with lithium through plasma discharge in a solution, and annealing the lithium-carbon composite in order to remove hydrogen from the lithium-carbon composite and form cavities in the lithium-carbon composite. Accordingly, a lithium-carbon composite can be simply synthesized using plasma discharge in a solution, and the synthesized lithium-carbon composite can be annealed to thus form cavities therein, thereby increasing the lithium charge and discharge performance of a lithium secondary battery using the lithium-carbon composite.

Abstract: A semiconductor device for monitoring a reverse voltage is provided. The semiconductor device includes an intellectual property having an input node and an output node; a passive component connected between the output node and a potential; a monitoring circuit connected to the input node and the output node and powered by a driving power, the monitoring circuit monitoring a difference between an input level at the input node and an output level at the output node to detect a reverse voltage across the intellectual property. The driving power is provided by the output node.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.

Abstract: Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.

Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.

Abstract: Provided are a semiconductor circuit and a semiconductor system. A semiconductor circuit includes a bandgap reference voltage generation circuit including an operational amplifier to amplify a differential voltage between a first node and a second node; a first startup circuit which receives input of an output signal of the operational amplifier from an output voltage node of the bandgap reference voltage generation circuit and pulls up the second node; and a second startup circuit which pulls down the output voltage node.

Abstract: A semiconductor device for monitoring a reverse voltage is provided. The semiconductor device includes an intellectual property having an input node and an output node; a passive component connected between the output node and a potential; a monitoring circuit connected to the input node and the output node and powered by a driving power, the monitoring circuit monitoring a difference between an input level at the input node and an output level at the output node to detect a reverse voltage across the intellectual property. The driving power is provided by the output node.

Abstract: An apparatus having an erase controller configured to perform a two-sided gate-induced drain leakage (GIDL) erase of non-volatile memory cells is disclosed. The erase controller is configured to apply a first voltage pulse having a first value for a voltage pulse attribute to the first end of a first pathway. The erase controller is configured to apply a second voltage pulse having a second value for the voltage pulse attribute to the first end of a second pathway. The first value and the second value are configured to compensate for different impedances such that a first erase voltage at a first select transistor is substantially symmetric with a second erase voltage at a second select transistor.

Abstract: An apparatus comprising strings of non-volatile memory cells, a first set of pathways connected to the strings, and a second set of pathways connected to the strings. The first set of pathways have first impedances that depend on location of respective strings. The second set of pathways having second impedances. The apparatus also includes one or more control circuits configured to compensate for location dependent impedance mismatch between the first set of pathways and the second set of pathways during memory operations on the non-volatile memory cells.

Abstract: An apparatus having an erase controller configured to perform a two-sided gate-induced drain leakage (GIDL) erase of non-volatile memory cells is disclosed. The erase controller is configured to apply a first voltage pulse having a first value for a voltage pulse attribute to the first end of a first pathway. The erase controller is configured to apply a second voltage pulse having a second value for the voltage pulse attribute to the first end of a second pathway. The first value and the second value are configured to compensate for different impedances such that a first erase voltage at a first select transistor is substantially symmetric with a second erase voltage at a second select transistor.

Abstract: An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.

Abstract: A CMOS temperature sensor is provided. The CMOS temperature sensor, comprises: a bandgap reference circuit outputting a constant bandgap reference voltage regardless of temperature using a first voltage inversely proportional to temperature and a second voltage proportional to temperature and generating a first current proportional to temperature using the second voltage; a reference voltage generator copying the first current and outputting a reference voltage generated using the first voltage and the copied first current; and a temperature information voltage generator copying the first current and outputting a temperature information voltage proportional to temperature.