Abstract: Provided is a complex patterning device. The complex patterning device includes a patterning module, on which a master substrate including a master pattern that contacts and is separated from a target substrate and which forms a plurality of target patterns having a reverse image of the master pattern on the target substrate by applying a pressure onto the target substrate, and a punching module including a punching mold that contacts and is separated from the target substrate, in which the plurality of target patterns are formed, and which divides at least any one of the plurality of target patterns by applying a pressure onto the target substrate.

Abstract: A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a plurality of non-volatile memory cells, a first pathway connected to the plurality of non-volatile memory cells, a second pathway connected to the plurality of non-volatile memory cells, and a control circuit connected to the first pathway and the second pathway. The control circuit is configured to compensate based on temperature for a temperature dependent impedance mismatch between the first pathway and the second pathway during a memory operation on the plurality of non-volatile memory cells.

Abstract: Through-substrate via structures are formed in a semiconductor substrate of a first semiconductor die. Semiconductor devices, dielectric material layers, and metal interconnect structures are formed over a front surface of the semiconductor substrate. A backside dielectric layer is formed on a backside surface. Integrated line and pad structures are formed over the backside dielectric layer on a respective through-substrate via structure. Each of the integrated line and pad structures includes a respective pad portion and respective line portion that extends from a center region of the backside surface to toward a periphery of the backside surface. A bonded assembly including the first semiconductor die and a second semiconductor die can be formed. Bonding pads can be provided in a center region of the interface between the semiconductor dies to facilitate power and signal distribution in the second semiconductor die with less electrical wiring.

Abstract: The present disclosure relates to an apparatus and a method for measuring miscibility in oil using back titration. The apparatus includes: a flocculation solution storage unit; a flow cell including a UV transmitting member; a dissolving agent storage unit; a UV irradiation unit; and a measurement unit, wherein: a flocculation solution is stored in the flocculation solution storage unit; the flocculation solution circulates between the flocculation solution storage unit and the flow cell; the measurement unit measures the UV transmittance of the flocculation solution while the dissolving agent in the dissolving agent storage unit is supplied to the flocculation solution storage unit; the miscibility in the oil is calculated from the amount of dissolving agent supplied and a change in the UV transmittance measured by the measurement unit; and the miscibility is calculated based on a time point when the slope of increase in the UV transmittance changes.

Abstract: A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad. Connectivity detection circuits test electrical connectivity between the third test pad and the fourth test pad.

Abstract: Disclosed herein are a calcium salts-supported metal catalyst, a method for preparing the same, and a method for the hydrodeoxygenation reaction of oxygenates using the same. The catalyst, in which a metal catalyst is supported on a carrier of a calcium salt, for example, calcium carbonate, has the effect of increasing the efficiency of hydrodeoxygenation reaction of oxygenates.

Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures.

Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures.

Abstract: Disclosed herein are a calcium salts-supported metal catalyst, a method for preparing the same, and a method for the hydrodeoxygenation reaction of oxygenates using the same. The catalyst, in which a metal catalyst is supported on a carrier of a calcium salt, for example, calcium carbonate, has the effect of increasing the efficiency of hydrodeoxygenation reaction of oxygenates.

Abstract: A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a plurality of non-volatile memory cells, a first pathway connected to the plurality of non-volatile memory cells, a second pathway connected to the plurality of non-volatile memory cells, and a control circuit connected to the first pathway and the second pathway. The control circuit is configured to compensate based on temperature for a temperature dependent impedance mismatch between the first pathway and the second pathway during a memory operation on the plurality of non-volatile memory cells.

Abstract: An apparatus for erasing non-volatile storage elements in a non-volatile memory system is disclosed. The apparatus has consistent speed in gate induced drain leakage (GIDL) erase across the operating temperature of the memory system. In one aspect, a voltage source outputs an erase voltage to NAND strings. The NAND strings may draw a GIDL erase current in response to the erase voltage. The amount of GIDL erase current for a given erase voltage is highly temperature dependent. The GIDL erase current may be sampled, and the erase voltage regulated based on the GIDL erase current. Therefore, the GIDL erase current, as well as erase speed, may be kept uniform across operating temperatures.

Abstract: An apparatus comprising strings of non-volatile memory cells, a first set of pathways connected to the strings, and a second set of pathways connected to the strings. The first set of pathways have first impedances that depend on location of respective strings. The second set of pathways having second impedances. The apparatus also includes one or more control circuits configured to compensate for location dependent impedance mismatch between the first set of pathways and the second set of pathways during memory operations on the non-volatile memory cells.

Abstract: A semiconductor device for monitoring a reverse voltage is provided. The semiconductor device includes an intellectual property having an input node and an output node; a passive component connected between the output node and a potential; a monitoring circuit connected to the input node and the output node and powered by a driving power, the monitoring circuit monitoring a difference between an input level at the input node and an output level at the output node to detect a reverse voltage across the intellectual property. The driving power is provided by the output node.

Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.

Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.

Abstract: A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: Provided is a complex patterning device. The complex patterning device includes a patterning module, on which a master substrate including a master pattern that contacts and is separated from a target substrate and which forms a plurality of target patterns having a reverse image of the master pattern on the target substrate by applying a pressure onto the target substrate, and a punching module including a punching mold that contacts and is separated from the target substrate, in which the plurality of target patterns are formed, and which divides at least any one of the plurality of target patterns by applying a pressure onto the target substrate.

Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.

Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.