Abstract: A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells. A size of a redundancy cell array of a first memory area is greater than a size of the redundancy cell arrays of the other memory areas.

Abstract: An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

Abstract: A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node.

Abstract: By using the combination of a pre-existing command signal that is common to two memory devices and a non-shared command signal that is applied individually to each of the devices, embodiments of the invention may operate in a mirror mode, thereby preventing unwanted signal degradation due to stub loads. Because embodiments of the invention do not require additional dedicated pins and/or pads compared to the conventional art, it is possible to achieve mirror mode operation in a smaller device package.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A semiconductor integrated circuit and method for burn-in-testing are provided that uniformly apply stress to elements of the semiconductor integrated circuit in a burn-in test mode, even when packaged. The semiconductor integrated circuit may include a transmission control unit that transmits an operation signal in a normal operating mode and blocks the operation signal in the test mode; and a test control unit that sequentially outputs a first signal and a second signal to an input/output (I/O) circuit in the test mode.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A semiconductor memory device that includes a memory cell connected to a wordline and a wordline voltage generator. The wordline voltage generator supplies a first negative voltage to the wordline in a standby state and supplies a second negative voltage that is lower with respect to ground than the first negative voltage to the wordline in a refresh operation. Accordingly, a leakage current generated at a transistor of a memory cell by gate-induced drain leakage (GIDL) is suppressed to enhance the performance of a refresh operation.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

Abstract: A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

Abstract: Example embodiments relate to a line defect detection circuit, including a first driver disposed at one end of a line and configured to drive the line using a first voltage or a second voltage in response to a control signal, and a second driver disposed at the other end of the line and configured to drive the line using the second voltage in response to a stress signal.

Abstract: Example embodiments of the present invention include a memory device testable without using data and a dataless test method. The memory device includes a plurality of registers to store test patterns, the registers being coupled to input/output DQ pads. The test patterns are stored in the registers when a mode register of the memory device is set. The memory device transfers the test patterns to a DQ pad responsive to a write test signal, and transfers the test patterns from the DQ pad to a data input buffer responsive to a read test signal. The memory device writes the test patterns transferred to the data input buffer to memory cells. The memory device reads data stored in the memory cells responsive to the write test signal and transfers the memory cell data from the DQ pad to a comparator responsive to the read test signal. The memory device compares the test patterns to the memory cell data transferred to the comparator and generates an indicator signal to indicate the comparison result.

Abstract: A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells. A size of a redundancy cell array of a first memory area is greater than a size of the redundancy cell arrays of the other memory areas.

Abstract: A memory system having a stub-bus configuration transmits a free-running clock through the same path as data signals. A single clock domain is employed for both read and write operations. For both operations, the read or write clock signal is routed through the same transmission path as the data, thereby increasing system transfer rates by maximizing the window of data validity. In this manner, data bus utilization is increased due to the elimination of a need for a preamble interval for the strobe signal, and pin count on the memory module connectors is therefore reduced.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.