Abstract: Provided is a stack type semiconductor package. The semiconductor package includes a first substrate, a first semiconductor chip, a second substrate, at least one second semiconductor chip and at least one third substrate. The first substrate has external connection terminals mounted on a first surface and a plurality of lands on a second surface that is an opposite side of the first surface. The first semiconductor chip is mounted on the second surface of the first substrate. The second substrate is attached at its first surface to the first semiconductor chip and includes plural outer lands in an outer perimeter of the second surface that is the opposite side of the first surface, a window penetrating between the first and second surface, inner lands around the window of the second surface. The second semiconductor chip is mounted on the second surface of the second substrate.

Abstract: By using the combination of a pre-existing command signal that is common to two memory devices and a non-shared command signal that is applied individually to each of the devices, embodiments of the invention may operate in a mirror mode, thereby preventing unwanted signal degradation due to stub loads. Because embodiments of the invention do not require additional dedicated pins and/or pads compared to the conventional art, it is possible to achieve mirror mode operation in a smaller device package.

Abstract: A semiconductor memory device having a hierarchical input/output architecture, includes a direct sense amplifier which is implemented without increasing the chip area and the number of interconnection lines of the device. The semiconductor memory device includes a pair of write control switches which are connected between a pair of local input/output lines and a pair of global input/output lines, and which connect the pair of local input/output lines and the pair of global input/output lines in response to a write control signal. Also, the semiconductor memory device includes a direct sense amplifier which is connected to the pair of local input/output lines and the pair of global input/output lines and generates a voltage difference, corresponding to a voltage difference between the pair of local input/output lines, between the pair of global input/output lines in response to a read control signal.

Abstract: Provided are a repair apparatus and method in a semiconductor memory device, the repair apparatus being selectively programmed suitable for a wafer-level test or a post package test. The repair apparatus includes a repair control circuit, a redundancy memory cell array, and a redundancy decoder. The repair control circuit programs one of an address signal for a first defective cell of the main memory cell array and an address signal for a second defective cell of the main memory cell array and outputs a control signal in response to the address signal undergoing the first decoding operation, the first defective cell being detected during a wafer-level test and the second defective cell being detected during a post package test. The redundancy memory cell array includes a plurality of redundancy memory cells and is activated to repair one of the first and second defective cells.

Abstract: A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.

Abstract: A clocking system and method in a point-to-point bus configuration overcomes the limitations of conventional approaches. In one embodiment, the present invention ensures the same phase relationship for the write clock in the write direction for all data transfers between modules, and similarly the same phase relationship for the read clock in the read direction for all data transfers between modules, regardless of module location. In another embodiment, on a given module, all transfers of data between a data buffer and a memory device in both read and write directions are clocked by a read clock signal and a write clock signal that have the same phase relationship and have the same propagation delay as the data bus between the buffer and the memory device.

Abstract: The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

Abstract: An active termination circuit is mounted in a memory circuit and includes a termination resistor which provides a termination resistance for the memory circuit, and a control circuit which receives an externally supplied active termination control signal, and which selectively switches on and off the termination resistor in response to the active termination control signal. The control circuit includes a synchronous input buffer and an asynchronous input buffer which each receive the active termination control signal, and a switching circuit which selectively outputs an output of said synchronous input buffer or an output of said asynchronous input buffer according to an operational mode of the memory circuit. The output of the switching circuit controls an on/off state of said termination resistor.

Abstract: Provided are a repair apparatus and method in a semiconductor memory device, the repair apparatus being selectively programmed suitable for a wafer-level test or a post package test. The repair apparatus includes a repair control circuit, a redundancy memory cell array, and a redundancy decoder. The repair control circuit programs one of an address signal for a first defective cell of the main memory cell array and an address signal for a second defective cell of the main memory cell array and outputs a control signal in response to the address signal undergoing the first decoding operation, the first defective cell being detected during a wafer-level test and the second defective cell being detected during a post package test. The redundancy memory cell array includes a plurality of redundancy memory cells and is activated to repair one of the first and second defective cells.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: Provided is a stack type semiconductor package. The semiconductor package includes a first substrate, a first semiconductor chip, a second substrate, at least one second semiconductor chip and at least one third substrate. The first substrate has external connection terminals mounted on a first surface and a plurality of lands on a second surface that is an opposite side of the first surface. The first semiconductor chip is mounted on the second surface of the first substrate. The second substrate is attached at its first surface to the first semiconductor chip and includes plural outer lands in an outer perimeter of the second surface that is the opposite side of the first surface, a window penetrating between the first and second surface, inner lands around the window of the second surface. The second semiconductor chip is mounted on the second surface of the second substrate.

Abstract: Provided are an apparatus which provides termination with respect to signals transmitted through a bus line, and a memory system using the apparatus which can prevent the number of sockets from increasing and a continuity module from being used. The termination providing apparatus includes a termination resistor having one end connected to a termination voltage, and is configured in a concave form to be mounted on an upper end of a memory module or in a convex form to be mounted in a socket. The memory system employs the termination providing apparatus, that is, a concave termination cap mounted on an upper end of a memory module, a convex termination cap mounted in a socket, and a top bus extension component mounted on upper ends of two memory modules and forming signal routing between the two memory modules.

Abstract: An integrated circuit memory device for use in a memory system receives predetermined command/address signals from a memory controller and reads and writes data in response to the command/address signals. The memory device includes at least one input/output terminal that inputs/outputs data from/to the memory controller via a data input/output bus, at least one termination resistor, and an active termination control signal generator that generates a control signal to control active termination of the at least one data input/output terminal in response to a chip selection signal from the memory controller.

Abstract: The semiconductor memory device includes a selecting circuit for selectively changing the mapping of address information to rows of normal and redundant memory cells. By controlling the operation of the selecting circuit, a row of normal memory cells including a defective memory cell can be replaced with an available row of non-defective redundant memory cells even if the row of redundant memory cells is not usually associated with the row of normal memory cells being replaced.

Abstract: An active termination circuit is mounted in a memory circuit and includes a termination resistor which provides a termination resistance for the memory circuit, and a control circuit which receives an externally supplied active termination control signal, and which selectively switches on and off the termination resistor in response to the active termination control signal. The control circuit includes a synchronous input buffer and an asynchronous input buffer which each receive the active termination control signal, and a switching circuit which selectively outputs an output of said synchronous input buffer or an output of said asynchronous input buffer according to an operational mode of the memory circuit. The output of the switching circuit controls an on/off state of said termination resistor.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A memory module device for use in a high frequency operation provides for ease in synchronization. In one example, the memory module includes integrated buffers, each having first and second data ports connected to respective data buses in a point-to-point configuration, such that data input through either data port of the first and second data ports is transferred to the memory device and is simultaneously output through the other data port of the first and second data ports. The integrated buffers each further include first and second command address ports connected to respective command address buses in a point-to-point configuration, such that a command address signal input through either port of the first and second command address ports is transferred to the memory device and simultaneously output through the other command address port of the first and second command address ports.

Abstract: An active termination circuit is mounted in a memory circuit and includes a termination resistor which provides a termination resistance for the memory circuit, and a control circuit which receives an externally supplied active termination control signal, and which selectively switches on and off the termination resistor in response to the active termination control signal. The control circuit includes a synchronous input buffer and an asynchronous input buffer which each receive the active termination control signal, and a switching circuit which selectively outputs an output of said synchronous input buffer or an output of said asynchronous input buffer according to an operational mode of the memory circuit. The output of the switching circuit controls an on/off state of said termination resistor.

Abstract: A memory system, memory module and memory device are described. The memory system includes a plurality of the memory modules connected in a series configuration on a first signal path. The first signal path and a second signal path carry memory control and data signals between the memory modules and a memory controller. The memory controller transmits and receives the control signals and data signals on the first and second signal paths. The first and second signal paths are connected together such that the memory modules are connected in a ring configuration. The control signals and data signals travel in opposite directions on the first and second signal paths. The first and second signal paths are shared by both the data signals and the control signals. The memory modules include multi-functional ports, each of which can receive both the control signals and the data signals and re-drive the signals onto the connected signal paths.

Abstract: A semiconductor memory device having a hierarchical structure of data input/output lines and a precharge method thereof. A precharge method in a semiconductor memory device having a hierarchical structure includes precharging the global input/output line pairs with half of a memory cell array voltage, and precharging the local input/output line pairs with the half of the memory cell array voltage.