Abstract: A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node.

Abstract: A semiconductor memory device having a mode control circuit includes a mode entrance portion for outputting an output signal in response to an external control signal, a mode entrance control portion for generating a mode entrance enable signal, MDEN, for controlling entry by the semiconductor device into a specific mode, for example a test mode, and a logic portion for combining the two to generate a mode signal for setting the specific mode. The mode entrance control portion includes a first and second fusing portion each including a fuse and a power-up signal for activating the MDEN in a case where the first and second fuses are maintained at an initial state or are changed at the initial state, and deactivating the MDEN otherwise. The mode control circuit prevents improper entry into the specific mode.

Abstract: A semiconductor memory device having a hierarchical input/output architecture, includes a direct sense amplifier which is implemented without increasing the chip area and the number of interconnection lines of the device. The semiconductor memory device includes a pair of write control switches which are connected between a pair of local input/output lines and a pair of global input/output lines, and which connect the pair of local input/output lines and the pair of global input/output lines in response to a write control signal. Also, the semiconductor memory device includes a direct sense amplifier which is connected to the pair of local input/output lines and the pair of global input/output lines and generates a voltage difference, corresponding to a voltage difference between the pair of local input/output lines, between the pair of global input/output lines in response to a read control signal.

Abstract: A memory system and a semiconductor memory device, which are capable of increasing memory bus efficiency and a refresh method of the semiconductor memory device are provided. A method for refreshing an open bank of a semiconductor memory device with a memory controller in a memory system including a plurality of semiconductor memory devices and the memory controller for controlling the plurality of semiconductor memory devices includes (a) applying a refresh command to each of the plurality of semiconductor memory device in order to the open bank; (b) precharging the open bank with each of the plurality of semiconductor memory devices if the refresh command is applied to the each of the plurality of semiconductor memory devices; and (c) refreshing the precharged bank with each of the plurality of semiconductor memory devices.

Abstract: An active termination circuit is mounted in a memory circuit and includes a termination resistor which provides a termination resistance for the memory circuit, and a control circuit which receives an externally supplied active termination control signal, and which selectively switches on and off the termination resistor in response to the active termination control signal. The control circuit includes a synchronous input buffer and an asynchronous input buffer which each receive the active termination control signal, and a switching circuit which selectively outputs an output of said synchronous input buffer or an output of said asynchronous input buffer according to an operational mode of the memory circuit. The output of the switching circuit controls an on/off state of said termination resistor.

Abstract: A memory system, which is capable of increasing the utilization efficiency of a semiconductor memory device, and a method of refreshing the semiconductor memory device are provided. The memory controller can selectively perform a refresh operation on a particular bank by applying a refresh command without also applying a bank address, and thus it is possible to increase the utilization efficiency of a semiconductor memory device.

Abstract: A semiconductor memory device having first and second memory architectures with different structures and allowing the possibility of selecting any one of the first and second memory architectures using a selection process and a memory system using the semiconductor memory device are provided. The first memory architecture has p banks, a page size of m/2 bytes of m/2 memory cells connected to one word line in each of the banks, and n/2 data terminals DQ. The second memory architecture has p banks, a page size of m bytes, and n data terminals. The option process may be realized by a bonding, a mask pattern, or a fuse. In a memory device, the page size and the number of memory banks are adjusted by a design option. Thus, the memory architecture is modified, redundancy flexibility is increased and power consumption is reduced.

Abstract: A memory device is adapted for prefetching data. The memory device has a memory cell array, with local sense amplifiers for receiving data bits prefetched from the memory cell array. The memory device also includes a serializer, and data paths that connect the local sense amplifiers to the serializer. Crossover connections are interposed between stages of the data paths. These transfer data bits between the data paths. Preferably they do that as part of being gates between the stages, which are in turn controlled by a clock. This way ordering is distributed within the data paths, and thus does not limit how fast the clock may become. In addition, the space used remains at a fundamental minimum.

Abstract: A step height between first and second elevated conductive lines that are laterally spaced apart on an integrated circuit substrate may be reduced by forming a dummy conductive line beneath the second conductive line, to further elevate the second conductive line on the integrated circuit substrate. Depth-of-focus may thereby be improved so that reliability of the conductive lines may also be improved. The second conductive line and the dummy conductive line vertically overlap by an amount that is less than one half the width of the second conductive line. Thus, the capacitance between the second conductive line and the dummy conductive line may be reduced. Undue delay therefore need not be created by introduction of the dummy conductive line.

Abstract: An integrated circuit memory device for use in a memory system receives predetermined command/address signals from a memory controller and reads and writes data in response to the command/address signals. The memory device includes at least one input/output terminal that inputs/outputs data from/to the memory controller via a data input/output bus, at least one termination resistor, and an active termination control signal generator that generates a control signal to control active termination of the at least one data input/output terminal in response to a chip selection signal from the memory controller.

Abstract: A memory system and a semiconductor memory device, which are capable of increasing memory bus efficiency and a refresh method of the semiconductor memory device are provided. A method for refreshing an open bank of a semiconductor memory device with a memory controller in a memory system including a plurality of semiconductor memory devices and the memory controller for controlling the plurality of semiconductor memory devices includes (a) applying a refresh command to each of the plurality of semiconductor memory device in order to the open bank; (b) precharging the open bank with each of the plurality of semiconductor memory devices if the refresh command is applied to the each of the plurality of semiconductor memory devices; and (c) refreshing the precharged bank with each of the plurality of semiconductor memory devices.

Abstract: A memory system, which is capable of increasing the utilization efficiency of a semiconductor memory device, and a method of refreshing the semiconductor memory device are provided. The memory system includes: a plurality of semiconductor memory devices, each of which comprises a plurality of banks, and wherein each memory device generates the address of a bank to be refreshed next and the address of a wordline to be refreshed as a first refreshed bank address and a refreshed row address, respectively, and refreshes a wordline of a bank corresponding to the first refreshed bank address and the refreshed row address; and a memory controller which generates and outputs the refresh command to the plurality of semiconductor memory devices and generates a second refreshed bank address, which is the same as the first refreshed bank address, in response to the refresh command.

Abstract: A mode control circuit for a semiconductor device and a semiconductor memory device having the same include a mode entrance portion for outputting an output signal in response to an external control signal, a mode entrance control portion for generating a mode entrance enable signal for controlling entry by the semiconductor device into a specific mode, for example a test mode, and a logic portion for logically combining the output signal of the mode entrance portion and the mode entrance enable signal to generate a mode signal for setting the specific mode.

Abstract: A chip information output circuit including a fuse box, capable of reducing a layout area without affecting input capacitance, is provided. The chip information output circuit includes a plurality of fuse blocks for generating different outputs according to whether a fuse is cut and a pipeline circuit for receiving a plurality of signals, which are output in parallel from the respective fuse blocks, and serially outputting the plurality of signals. Each of the fuse blocks includes a plurality of fuse boxes for generating output signals, the levels of which are either a high or low logic level according to whether the fuses included therein are cut, wherein the respective fuse boxes are enabled in response to the respective control signals and the output lines of the fuse boxes are wired by an OR operation. The pipeline circuit includes a plurality of serially connected latch units for latching signals output from the fuse blocks and outputting the latched signals.

Abstract: Integrated circuit devices and methods of operating same include a delayed locked loop (DLL) circuit that can be operated at a high frequency during a normal operation mode and during a test mode. The test mode may be, for example, for performing burn-in testing. For example, an integrated circuit device may include a DLL control circuit that generates a control signal that is responsive to a test mode signal. An oscillator circuit may generate a clock signal that is responsive to the test mode signal. This clock signal may be a high frequency clock signal, such as that used to drive a DLL circuit during a normal operation mode. A DLL circuit, which is responsive to the clock signal, may be configured to operate in either a test mode or a normal operation mode based on the control signal. By generating the clock signal at a high frequency, the DLL circuit may be evaluated during burn-in testing, for example, under conditions that are comparable to conditions during normal operation.

Abstract: A memory system having a stub-bus configuration transmits a free-running clock through the same path as data signals. A single clock domain is employed for both read and write operations. For both operations, the read or write clock signal is routed through the same transmission path as the data, thereby increasing system transfer rates by maximizing the window of data validity. In this manner, data bus utilization is increased due to the elimination of a need for a preamble interval for the strobe signal, and pin count on the memory module connectors is therefore reduced.

Abstract: A memory device is adapted for prefetching data. The memory device has a memory cell array, with local sense amplifiers for receiving data bits prefetched from the memory cell array. The memory device also includes a serializer, and data paths that connect the local sense amplifiers to the serializer. Crossover connections are interposed between stages of the data paths. These transfer data bits between the data paths. Preferably they do that as part of being gates between the stages, which are in turn controlled by a clock. This way ordering is distributed within the data paths, and thus does not limit how fast the clock may become. In addition, the space used remains at a fundamental minimum.

Abstract: A step height between first and second elevated conductive lines that are laterally spaced apart on an integrated circuit substrate may be reduced by forming a dummy conductive line beneath the second conductive line, to further elevate the second conductive line on the integrated circuit substrate. Depth-of-focus may thereby be improved so that reliability of the conductive lines may also be improved. The second conductive line and the dummy conductive line vertically overlap by an amount that is less than one half the width of the second conductive line. Thus, the capacitance between the second conductive line and the dummy conductive line may be reduced. Undue delay therefore need not be created by introduction of the dummy conductive line.

Abstract: A clocking system and method in a point-to-point bus configuration overcomes the limitations of conventional approaches. In one embodiment, the present invention ensures the same phase relationship for the write clock in the write direction for all data transfers between modules, and similarly the same phase relationship for the read clock in the read direction for all data transfers between modules, regardless of module location. In another embodiment, on a given module, all transfers of data between a data buffer and a memory device in both read and write directions are clocked by a read clock signal and a write clock signal that have the same phase relationship and have the same propagation delay as the data bus between the buffer and the memory device.

Abstract: Disclosed is a memory device, comprising a memory controller, a clock input pin for receiving a clock signal, a first chip selection signal input pin for receiving a first chip selection signal for a row address strobe from the memory controller, a second chip selection signal input pin for receiving a second chip selection signal for a column address strobe from the memory controller, a row command input pin for receiving a row command from the memory controller, a column command input pin for receiving a column command from the memory controller, a plurality of row address input pins for receiving row addresses from the memory controller, and a plurality of column address input pins for receiving column addresses from the memory controller.