Patents by Inventor Lakshminarayana Baba Arimilli
Lakshminarayana Baba Arimilli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10216653Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.Type: GrantFiled: October 3, 2017Date of Patent: February 26, 2019Assignee: International Busiess Machines CorporationInventors: Lakshminarayana Baba Arimilli, Yiftach Benjamini, Bartholomew Blaner, Daniel M. Dreps, John David Irish, David J. Krolak, Lonny Lambrecht, Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Kenneth M. Valk, Curtis C. Wollbrink
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Publication number: 20180095905Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.Type: ApplicationFiled: October 3, 2017Publication date: April 5, 2018Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: LAKSHMINARAYANA BABA ARIMILLI, YIFTACH BENJAMINI, BARTHOLOMEW BLANER, DANIEL M. DREPS, JOHN DAVID IRISH, DAVID J. KROLAK, LONNY LAMBRECHT, MICHAEL S. SIEGEL, WILLIAM J. STARKE, JEFFREY A. STUECHELI, KENNETH M. VALK, CURTIS C. WOLLBRINK
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Patent number: 9396021Abstract: A technique for operating a high performance computing cluster includes monitoring workloads of multiple processors. The high performance computing cluster includes multiple nodes that each include two or more of the multiple processors. Workload information for the multiple processors is periodically updated in respective local job tables maintained in each of the multiple nodes. Based on the workload information in the respective local job tables, one or more threads are periodically moved to a different one of the multiple processors.Type: GrantFiled: December 16, 2008Date of Patent: July 19, 2016Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Ravi Kumar Arimilli, Claude Basso, Jean L. Calvignac
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Patent number: 9384042Abstract: A technique for operating a high performance computing (HPC) cluster includes monitoring communication between threads assigned to multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more of the threads are moved to a different one of the multiple processors based on the communication between the threads.Type: GrantFiled: December 16, 2008Date of Patent: July 5, 2016Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Ravi Kumar Arimilli, Claude Basso, Jean L. Calvignac
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Patent number: 9336145Abstract: A technique for performing cache injection includes monitoring, at a host fabric interface, snoop responses to an address on a bus. When the snoop responses indicate a data block associated with the address is in a shared state, input/output data associated with the address on the bus is directed to a cache that includes the data block in the shared state and is located physically closer to the host fabric interface than one or more other caches that include the data block associated with the address in the shared state.Type: GrantFiled: April 9, 2009Date of Patent: May 10, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lakshminarayana Baba Arimilli, Ravi K. Arimilli, Jody B. Joyner, William J. Starke
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Patent number: 9268703Abstract: A technique for performing cache injection in a processor system includes monitoring, by a cache, addresses on a bus. Input/output data associated with an address of a data block stored in the cache is then requested from a remote node, via a network controller. Ownership of the input/output data is acquired by the cache when an address on the bus that is associated with the input/output data corresponds to the address of the data block stored in the cache.Type: GrantFiled: April 15, 2009Date of Patent: February 23, 2016Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Ravi K. Arimilli, Jody B. Joyner, William J. Starke
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Patent number: 9256540Abstract: A technique for performing cache injection includes monitoring addresses on a bus in response to a cache injection instruction. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block associated with the cache injection instruction.Type: GrantFiled: September 18, 2008Date of Patent: February 9, 2016Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Ravi K. Arimilli, Balaram Sinharoy
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Patent number: 8443146Abstract: A technique for performing cache injection includes monitoring an instruction stream for a specific instruction sequence. Addresses on a bus are then monitored, at a cache, in response to detecting the specific instruction sequence a determined number of times. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.Type: GrantFiled: September 18, 2008Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Ravi K. Arimilli, Balaram Sinharoy
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Patent number: 8429349Abstract: A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement policy position of the data block is then modified (to increase a probability that the data block is consumed prior to ejection from the cache).Type: GrantFiled: September 18, 2008Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Ravi K. Arimilli, Balaram Sinharoy
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Patent number: 8281075Abstract: A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.Type: GrantFiled: April 14, 2009Date of Patent: October 2, 2012Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Brian Mitchell Bass, David Wayne Cummings, Bernard Charles Drerup, Guy Lynn Guthrie, Ronald Nick Kalla, Hugh Shen, Michael Steven Siegel, William John Starke, Derek Edward Williams
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Patent number: 8239524Abstract: A technique for operating a high performance computing (HPC) cluster includes monitoring workloads of multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more threads assigned to one or more of the multiple processors are moved to a different one of the multiple processors based on the workloads of the multiple processors.Type: GrantFiled: December 16, 2008Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Ravi Kumar Arimilli, Claude Basso, Jean L. Calvignac
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Patent number: 8122132Abstract: A technique for operating a high performance computing cluster (HPC) having multiple nodes (each of which include multiple processors) includes periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes. Respective local job tables maintained in each of the multiple nodes are updated based on the broadcast information. One or more threads are then moved from one or more of the multiple processors to a different one of the multiple processors (based on the broadcast information in the respective local job tables).Type: GrantFiled: December 16, 2008Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Ravi Kumar Arimilli, Claude Basso, Jean L. Calvignac
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Publication number: 20100268896Abstract: A technique for performing cache injection in a processor system includes monitoring, by a cache, addresses on a bus. Input/output data associated with an address of a data block stored in the cache is then requested from a remote node, via a network controller. Ownership of the input/output data is acquired by the cache when an address on the bus that is associated with the input/output data corresponds to the address of the data block stored in the cache.Type: ApplicationFiled: April 15, 2009Publication date: October 21, 2010Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: Lakshminarayana Baba Arimilli, Ravi K. Arimilli, Jody B. Joyner, William J. Starke
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Publication number: 20100262735Abstract: A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command (via the system bus) process the specific request-type command when the core permission controls are the same as the respective slave permission controls.Type: ApplicationFiled: April 14, 2009Publication date: October 14, 2010Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: Lakshminarayana Baba Arimilli, Brian Mitchell Bass, David Wayne Cummings, Bernard Charles Drerup, Guy Lynn Guthrie, Ronald Nick Kalla, Hugh Shen, Michael Steven Siegel, William John Starke, Derek Edward Williams
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Publication number: 20100262787Abstract: A technique for performing cache injection includes monitoring, at a host fabric interface, snoop responses to an address on a bus. When the snoop responses indicate a data block associated with the address is in a shared state, input/output data associated with the address on the bus is directed to a cache that includes the data block in the shared state and is located physically closer to the host fabric interface than one or more other caches that include the data block associated with the address in the shared state.Type: ApplicationFiled: April 9, 2009Publication date: October 14, 2010Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: Lakshminarayana Baba Arimilli, Ravi K. Arimilli, Jody B. Joyner, William J. Starke
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Publication number: 20100153542Abstract: A technique for operating a high performance computing cluster (HPC) having multiple nodes (each of which include multiple processors) includes periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes. Respective local job tables maintained in each of the multiple nodes are updated based on the broadcast information. One or more threads are then moved from one or more of the multiple processors to a different one of the multiple processors (based on the broadcast information in the respective local job tables).Type: ApplicationFiled: December 16, 2008Publication date: June 17, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lakshminarayana Baba Arimilli, Ravi Kumar Arimilli, Claude Basso, Jean L. Calvignac
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Publication number: 20100153965Abstract: A technique for operating a high performance computing (HPC) cluster includes monitoring communication between threads assigned to multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more of the threads are moved to a different one of the multiple processors based on the communication between the threads.Type: ApplicationFiled: December 16, 2008Publication date: June 17, 2010Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: Lakshminarayana Baba Arimilli, Ravi Kumar Arimilli, Claude Basso, Jean L. Calvignac
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Publication number: 20100153541Abstract: A technique for operating a high performance computing (HPC) cluster includes monitoring workloads of multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more threads assigned to one or more of the multiple processors are moved to a different one of the multiple processors based on the workloads of the multiple processors.Type: ApplicationFiled: December 16, 2008Publication date: June 17, 2010Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: Lakshminarayana Baba Arimilli, Ravi Kumar Arimilli, Claude Basso, Jean L. Calvignac
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Publication number: 20100153966Abstract: A technique for operating a high performance computing cluster includes monitoring workloads of multiple processors. The high performance computing cluster includes multiple nodes that each include two or more of the multiple processors. Workload information for the multiple processors is periodically updated in respective local job tables maintained in each of the multiple nodes. Based on the workload information in the respective local job tables, one or more threads are periodically moved to a different one of the multiple processors.Type: ApplicationFiled: December 16, 2008Publication date: June 17, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lakshminarayana Baba Arimilli, Ravi Kumar Arimilli, Claude Basso, Jean L. Calvignac
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Patent number: 6633838Abstract: The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis.Type: GrantFiled: November 4, 1999Date of Patent: October 14, 2003Assignee: International Business Machines CorporationInventors: Lakshminarayana Baba Arimilli, Michael Stephen Floyd, Larry Scott Leitner, Kevin F. Reick, Jennifer Lane Vargus