Abstract: A method and apparatus for casing out data within a cache memory hierarchy for a data processing system is disclosed. The data processing system has multiple processing units, each of the processing units having a multi-level cache memory hierarchy. The cache memory hierarchy includes a first cache and a second cache at a same cache level. Furthermore, the first cache and the second cache share a lower-level cache. In response to a castout write request from the first cache to the lower-level cache, the second cache aborts the data transfer for the castout write request if the second cache already has a copy of data of the castout write request. The coherency state of both the first and second caches are then updated.

Abstract: A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

Abstract: A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system.

Abstract: A method and apparatus for transmitting control signals within a hierarchial cache memory architecture of a data processing system is disclosed. The cache memory hierarchy includes multiple levels of cache memories, each level may have a different size and speed. In response to a processor request for information, a control command is sent to the cache memory hierarchy. The control command includes multiple control blocks. Beginning at the lowest possible cache level of the cache memory hierarchy, a determination is made whether or not there is a cache hit at a current level of the cache memory hierarchy. In response to a determination that there is not a cache hit at the current level, an abbreviated control command is sent to an upper cache level of the cache memory hierarchy, after a control block that corresponds to the current level is removed from the control command.

Abstract: A method and apparatus for casting out data within a cache memory hierarchy for a data processing system is disclosed. The data processing system has multiple processing units, each of the processing units having a multi-level cache memory hierarchy. In response to a castout write request from a cache memory to a non-inclusive lower-level cache memory within a cache memory hierarchy, the data transfer is aborted if the lower-level cache memory already has a copy of the data of the castout write. The coherency state of the lower-level cache memory is then updated, if necessary.