Abstract: A low-inductance capacitor exhibits a first characteristic inductance during use in a first capacitor subsection and a second characteristic inductance during use in a second capacitor subsection, and the first and second characteristic inductances act to neutralize each other. A process of forming the low-inductance capacitor includes heat curing. A package includes a low-inductance capacitor and a mounting substrate.

Abstract: An integrated circuit including an interlayer dielectric which may be prone to failure due to processing conditions may be protected by coupling the integrated circuit to a substrate through a solder ball over a conductive polymer. The conductive polymer allows conduction of electrical current to or from the integrated circuit and also provides cushioning against stresses including both mechanical perturbations and thermal expansion and contraction. As a result, relatively lower dielectric constant materials may be utilized as interlayer dielectrics within the integrated circuit.

Abstract: A structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.

Abstract: In one embodiment, a structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.

Abstract: A method for forming a split thin film capacitor for providing multiple power and reference supply voltage levels to electrical devices such as integrated circuits, may be useful in space restricted applications, and in applications that require very close electrical connections between the power consumer and the power supply. An example of both a space restricted application and a close coupling application may be an integrated circuit such as a microprocessor, that may need a closely coupled capacitor supplying and moderating power to the microprocessor in order to quickly respond to instantaneous power demands that may be found in high clock rate devices. The method may supply a lower voltage power supply level for minimum sized transistors in the fast core logic portions of the microprocessor, and a higher voltage power supply level for the cache memory and I/O transistors.

Abstract: A capacitor with reduced equivalent series resistance and reduces equivalent series inductance is provided. Capacitors are provided with multiple plate assemblies that couple to a common single first polarity terminal. Capacitors are also provided with multiple plate assemblies that each couple to a respective second polarity terminal. Fan-like plate assemblies are arranged to provide increased capacitance with reduced equivalent series resistance and reduces equivalent series inductance. Capacitors are provided that mount using surface mounting technology. Capacitors are provided that conform to existing capacitor form factors.

Abstract: In an embodiment, an electrolytic polymer capacitor includes a metal first electrode and a polymer-containing second electrode.

Abstract: An electronic device includes a material having a first dielectric constant (K) value, and a material having a second dielectric constant (K) value. The first dielectric constant (K) value is lower than the second dielectric constant (K) value. The electronic device also includes input/output connection conductors for transmitting signals to and from a die. The input/output connection conductors are routed through the material of the interposer having the first dielectric constant. The electronic device also includes power connection conductors for delivering power to the die, and ground connection conductors. The power and ground connection conductors are routed through the material having the second dielectric constant.

Abstract: An apparatus having a first set of contacts on a first side of the apparatus adapted to interface with a corresponding plurality of contacts on an integrated circuit package. The apparatus further includes a second set of contacts on a second side of the apparatus adapted to interface with a corresponding plurality of grid array leads, and a plurality of capacitive storage structures coupled to the first and second sets of contacts.

Abstract: Some embodiments of the present invention include capacitors with controlled resistance.

Abstract: In one embodiment, a capacitor comprises a substrate defining a first electrical terminal; a catalyst layer disposed on the substrate; a plurality of carbon nanotubes disposed on the catalyst layer; a dielectric layer disposed over the plurality of carbon nanotubes; and a conductive layer disposed on the dielectric layer and defining a second electrical terminal.

Abstract: A base structure is formed from a green material having first and second opposing sides and having a plurality of via openings therein. The green material is then sintered so that the green material becomes a sintered ceramic material and the base structure becomes a sintered ceramic base structure having the via openings. A conductive via is formed in each via opening of the sintered ceramic base structure. First and second capacitor structures are formed on the sintered ceramic base structure, each on a respective side of the sintered ceramic base structure. The power and ground planes of the capacitor structure are connected to the vias. As such, a capacitor structure can be formed and connected to the vias without the need to drill via openings in brittle substrates such as silicon substrates. Capacitor structures on opposing sides provide more capacitance without manufacturing complexities associated with the manufacture of one capacitor structure having a large number of power and ground planes.

Abstract: A method and apparatus for supplying power to a load. The apparatus comprising a voltage regulator circuit and a controller coupled to the voltage regulator circuit. The controller to cause the voltage regulator circuit to maintain a first voltage for the load operating in the first mode. The controller to detect a change in the operating mode of the load and to cause the voltage regulator circuit to output a second voltage. Prior to causing the voltage regulator circuit to output a second voltage the controller may allow voltage and current to stabilize at the load at a value between the first mode and a second mode.

Abstract: A structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.

Abstract: A capacitor with low inductance connection terminals and having a first surface, includes a first electrode of porous metal, a dielectric layer formed on the porous metal, a second electrode formed on the dielectric layer, and a plurality of connection terminals electrically coupled to the first electrode on the first surface and a plurality of connection terminals electrically coupled to the second electrode on the first surface.

Abstract: A method and apparatus for supplying power to a load. The apparatus comprising a voltage regulator circuit and a controller coupled to the voltage regulator circuit. The controller to cause the voltage regulator circuit to maintain a first voltage for the load operating in the first mode. The controller to detect a change in the operating mode of the load and to cause the voltage regulator circuit to output a second voltage. Prior to causing the voltage regulator circuit to output a second voltage the controller may allow voltage and current to stabilize at the load at a value between the first mode and a second mode.

Abstract: A capacitor with low inductance connection terminals and having a first surface, includes a first electrode of porous metal, a dielectric layer formed on the porous metal, a second electrode formed on the dielectric layer, and a plurality of connection terminals electrically coupled to the first electrode on the first surface and a plurality of connection terminals electrically coupled to the second electrode on the first surface.

Abstract: A method of forming a capacitor with low inductance connection terminals, comprising a first surface including a first electrode of porous metal, forming a dielectric layer on the first electrode, forming a second electrode on the dielectric layer, attaching a plurality of electrically coupled connection terminals to the first electrode on the first surface and attaching a plurality of electrically coupled connection terminals to the second electrode on the first surface.

Abstract: An integrated circuit (IC) package process is provided that includes forming a first via hole in a first substrate. Patterning signal lines on a first surface and a second surface of the first substrate. Attaching a second substrate to the first surface of the first substrate. Electronically connecting a portion of the signal lines of the first substrate and the second substrate. Attaching an electrical element to the first surface of the first substrate. Forming a via hole in a third substrate. Introducing conductive material over a first surface and a second surface of the third substrate. Forming a second circuit pattern on the first surface and the second surface of the third substrate. Additionally, attaching the third substrate to the first substrate with a second layer of adhesive. In an alternative embodiment, a process includes forming a via hole in a first substrate.

Abstract: A capacitor with low inductance connection terminals and having a first surface, includes a first electrode of porous metal, a dielectric layer formed on the porous metal, a second electrode formed on the dielectric layer, and a plurality of connection terminals electrically coupled to the first electrode on the first surface and a plurality of connection terminals electrically coupled to the second electrode on the first surface.