Abstract: One illustrative transistor device disclosed herein includes, among other things, a gate positioned above a semiconductor substrate, the gate comprising a gate structure, a conductive source/drain metallization structure positioned adjacent the gate, the conductive source/drain metallization structure having a front face, and an insulating spacer that is positioned on and in contact with at least a portion of the front face of the conductive source/drain metallization structure. In this example, the device also includes a gate contact opening that exposes at least a portion of the insulating spacer and a portion of an upper surface of the gate structure and a conductive gate contact structure positioned in the gate contact opening, wherein the conductive gate contact structure contacts at least a portion of the insulating spacer and wherein the conductive gate contact structure is conductively coupled to the gate structure.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

Abstract: Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein the intervening metallization level (MX+1) is electrically isolated from the skip via. Cap layers in the metallization levels are pre-patterned to provide openings therein generally corresponding to locations of the skip via structure prior to high aspect ratio etching to form the skip via structure.

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above at least an active region, wherein the gate structure has an axial length in a direction corresponding to a gate width direction of the transistor device. In this example, a first portion of the axial length of the gate structure has a first upper surface and a second portion of the axial length of the gate structure has a second upper surface, wherein the first upper surface is positioned at a level that is above a level of the second upper surface. The device also includes a gate contact structure that contacts the first upper surface of the gate structure.

Abstract: One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.

Abstract: A method of forming a buried local interconnect is disclosed including, among other things, forming a first sacrificial layer embedded between a first semiconductor layer and a second semiconductor layer, forming a plurality of fin structures above the second semiconductor layer, forming a mask layer having an opening positioned between an adjacent pair of the fin structures, removing a portion of the second semiconductor layer exposed by the opening to expose the first sacrificial layer and define a first cavity in the second semiconductor layer, removing portions of the first sacrificial layer positioned between the first semiconductor layer and the second semiconductor layer to form lateral cavity extensions of the first cavity, forming a first liner layer in the first cavity, and forming a conductive interconnect in the first cavity over the first liner layer.

Abstract: A method of forming a buried local interconnect is disclosed including, among other things, forming a first sacrificial layer embedded between a first semiconductor layer and a second semiconductor layer, forming a plurality of fin structures above the second semiconductor layer, forming a mask layer having an opening positioned between an adjacent pair of the fin structures, removing a portion of the second semiconductor layer exposed by the opening to expose the first sacrificial layer and define a first cavity in the second semiconductor layer, removing portions of the first sacrificial layer positioned between the first semiconductor layer and the second semiconductor layer to form lateral cavity extensions of the first cavity, forming a first liner layer in the first cavity, and forming a conductive interconnect in the first cavity over the first liner layer.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Abstract: Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein the intervening metallization level (MX+1) is electrically isolated from the skip via. Cap layers in the metallization levels are pre-patterned to provide openings therein generally corresponding to locations of the skip via structure prior to high aspect ratio etching to form the skip via structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interrupted small block shape structures (e.g., cut metal lines forming cell boundaries) and methods of manufacture. The structure includes: a plurality of wiring lines with cuts that form a cell boundary; and at least one wiring line extending beyond the cell boundary and which is continuous from cell to cell.

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above at least an active region, wherein the gate structure has an axial length in a direction corresponding to a gate width direction of the transistor device. In this example, a first portion of the axial length of the gate structure has a first upper surface and a second portion of the axial length of the gate structure has a second upper surface, wherein the first upper surface is positioned at a level that is above a level of the second upper surface. The device also includes a gate contact structure that contacts the first upper surface of the gate structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.