Abstract: A design level compatible with a sidewall image transfer process employs an alternating grid of mandrel-type line tracks and non-mandrel-type line tracks. Target structure design shapes are formed such that all vertices of the target structure design shapes are on the grid. The target structure design shapes are classified as mandrel-type design shapes and non-mandrel-type design shapes depending on the track type of the overlapping line tracks for lengthwise portions. All mandrel-type line tracks and straps of the mandrel-type design shapes less lateral strap regions of the non-mandrel-type design shapes collectively form mandrel design shapes, which can be employed to generate a first lithographic mask. Sidewall design shapes are generated from the mandrel design shapes. Blocking shapes for a second lithographic mask can be generated by selecting all areas that are not included in the target structure design shapes or the sidewall design shapes.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for aligning a set of orthogonal circuit elements in an integrated circuit (IC) layout. In some embodiments, a computer-implemented method for aligning a set of orthogonal circuit elements in an IC layout includes: classifying each orthogonal circuit element in the set of orthogonal circuit elements as including a first space-designated edge and a second space-designated edge; and aligning each orthogonal circuit element on an edge placement grid according to the first space-designated edge and the second space-designated edge, the edge placement grid having a first set of space-designated grid lines separated by a first distance, and a second set of space-designated grid lines separated by a second distance, wherein the first set of space-designated grid lines is separated from the second set of space-designated grid lines by an offset distance.

Abstract: Methods of the present disclosure can include: using a computing device to perform actions including: applying a design rule check (DRC) on a proposed integrated circuit (IC) layout, wherein the DRC applies a set of restrictive design rules (RDRs) in response to the proposed IC layout being a contact area (CA) layout; computing a conflict graph for the proposed IC layout in response to one of the IC layout being a metal layer layout and the set of RDRs being satisfied; determining whether the IC layout is one of non-colorable, indeterminate, partially colorable, and fully colorable; and partially coloring the IC layout and identifying non-colorable nodes in response to the IC layout being indeterminate or partially colorable.

Abstract: A mechanism is provided in a data processing system for hierarchical triple patterning decomposition. The mechanism receives an integrated circuit design. The mechanism enforces boundary conditions on three-color mapping of shapes in a layer of the integrated circuit design at the cell level. The mechanism places cells in the layer of the integrated circuit design. The mechanism identifies post placement coloring conflicts and resolves the post placement coloring conflicts with two-color flipping in coloring runs containing one or more conflicts.

Abstract: A design level compatible with a sidewall image transfer process employs an alternating grid of mandrel-type line tracks and non-mandrel-type line tracks. Target structure design shapes are formed such that all vertices of the target structure design shapes are on the grid. The target structure design shapes are classified as mandrel-type design shapes and non-mandrel-type design shapes depending on the track type of the overlapping line tracks for lengthwise portions. All mandrel-type line tracks and straps of the mandrel-type design shapes less lateral strap regions of the non-mandrel-type design shapes collectively form mandrel design shapes, which can be employed to generate a first lithographic mask. Sidewall design shapes are generated from the mandrel design shapes. Blocking shapes for a second lithographic mask can be generated by selecting all areas that are not included in the target structure design shapes or the sidewall design shapes.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for aligning a set of orthogonal circuit elements in an integrated circuit (IC) layout. In some embodiments, a computer-implemented method for aligning a set of orthogonal circuit elements in an IC layout includes: classifying each orthogonal circuit element in the set of orthogonal circuit elements as including a first space-designated edge and a second space-designated edge; and aligning each orthogonal circuit element on an edge placement grid according to the first space-designated edge and the second space-designated edge, the edge placement grid having a first set of space-designated grid lines separated by a first distance, and a second set of space-designated grid lines separated by a second distance, wherein the first set of space-designated grid lines is separated from the second set of space-designated grid lines by an offset distance.

Abstract: Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.

Abstract: Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.

Abstract: In various embodiments, a method of designing an integrated circuit (IC) layout for a multiple patterning layout fill process includes: providing a pre-characterized mask tile library including a plurality of distinct mask tiles each having a distinct mask density on a plurality of distinct exposures each associated with a patterning process in the multiple patterning process; determining a density of a mask group in a first layout window in the IC layout, the first layout window including an open space unfilled by the mask group; and selecting a set of mask tiles from the plurality of distinct mask tiles to fill a portion of the open space, the selecting based upon the determined density of the mask group in the first layout window and the distinct mask density of the selected set of mask tiles on the plurality of distinct exposures.

Abstract: A method for decomposing design shapes in a design level into a plurality of target design levels is provided. Design shapes including first-type edges and second-type edges having different directions is provided for a design level. Inner vertices are identified and paired up. Vertices are classified into first-type vertices and second-type vertices. First mask level shapes are generated so as to touch the first-type vertices, and second mask level shapes are generated so as to tough the second-type vertices. Cut mask level shapes are generated to touch each first-type edges that are not over a second-type edge and to touch each second-type edges that are not over a first-type edge. Suitable edges are sized outward to ensure overlap among the various shapes. The design shapes are thus decomposed into first mask level shapes, the second mask level shapes, and the cut mask level shapes.

Abstract: A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction. The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features. The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A mechanism is provided for mask assignment for triple patterning lithography. The mechanism identifies tip-to-tip (TT), tip-to-side (TS), and side-to-side (SS) conflicting parts by design rule dependent projection. The mechanism finds stitch location for TT, TS, and SS conflicts separately. The mechanism colors TT, TS, and SS conflicting parts with mask0/mask1, mask0/mask2, mask1/mask2 coloring cycle with each type colored separately. The mechanism uses existing infrastructure of two-way coloring. As a first objective, the mechanism attempts to minimize conflicts. As a second objective, the mechanism attempts to minimize the number of stitches by assigning the two sides of stitches to the same mask. Once coloring of all conflicting parts is done, the mechanism colors non-conflicting parts to maximize minimum overlap of exposures and to use both colors if two sides are different colors and one color if both sides are the same color.

Abstract: A mechanism is provided for mask assignment for triple patterning lithography. The mechanism identifies tip-to-tip (TT), tip-to-side (TS), and side-to-side (SS) conflicting parts by design rule dependent projection. The mechanism finds stitch location for TT, TS, and SS conflicts separately. The mechanism colors TT, TS, and SS conflicting parts with mask0/mask1, mask0/mask2, mask1/mask2 coloring cycle with each type colored separately. The mechanism uses existing infrastructure of two-way coloring. As a first objective, the mechanism attempts to minimize conflicts. As a second objective, the mechanism attempts to minimize the number of stitches by assigning the two sides of stitches to the same mask. Once coloring of all conflicting parts is done, the mechanism colors non-conflicting parts to maximize minimum overlap of exposures and to use both colors if two sides are different colors and one color if both sides are the same color.

Abstract: A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction, The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features, The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors.

Abstract: A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker.

Abstract: A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.

Abstract: The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is modified by modifying a critical dimension so as to improve or optimize an electrical characteristic, while also ensuring that one or more yield constraints are satisfied. The use of an electrically optimized target can result in cost-effective mask designs that better meet the designers' intent.

Abstract: A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.

Abstract: A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.