Patents by Inventor Lars W. Liebmann
Lars W. Liebmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9768113Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.Type: GrantFiled: May 12, 2016Date of Patent: September 19, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, TOKYO ELECTRON LIMITED, STMICROELECTRONICS, INC.Inventors: Yannick Feurprier, Joe Lee, Lars W. Liebmann, Yann Mignot, Terry A. Spooner, Douglas M. Trickett, Mehmet Yilmaz
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Patent number: 9735054Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.Type: GrantFiled: June 7, 2016Date of Patent: August 15, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
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Publication number: 20170170070Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
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Publication number: 20170162438Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.Type: ApplicationFiled: February 14, 2017Publication date: June 8, 2017Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
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Patent number: 9627257Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.Type: GrantFiled: June 7, 2016Date of Patent: April 18, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
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Publication number: 20170104100Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventors: Emre Alptekin, Lars W. Liebmann, Injo Ok, Balasubramanian Pranatharthiharan, Ravikumar Ramachandran, Soon-Cheon Seo, Charan V.V.S. Surisetty, Mickey H. Yu
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Publication number: 20170092585Abstract: A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.Type: ApplicationFiled: December 13, 2016Publication date: March 30, 2017Inventors: Su Chen Fan, Lars W. Liebmann, Ruilong Xie
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Patent number: 9601513Abstract: Various embodiments include methods and integrated circuit structures. One method includes masking a structure with a mask to cover at least a portion of the structure under the mask, selectively implanting a material through a semiconductor layer and into a buried insulator layer forming an implant region. The implant region is substantially parallel to and below an upper surface of the structure. The method may also include masking an additional portion of the structure; etching a set of access ports though the semiconductor layer and partially through the insulator layer into the implant region; etching at least one tunnel below the upper surface of the structure in the implant region using the set of access; and depositing a conductor into the at least one tunnel and the set of access ports.Type: GrantFiled: December 22, 2015Date of Patent: March 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Terence B. Hook, Andreas Scholze, Lars W. Liebmann, Roger A. Quon, Andrew H. Simon
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Publication number: 20170061062Abstract: Improving reliability of an electronic device includes: determining whether a side space of an interconnect of the electronic device is available for a redundant interconnect, determining whether a line end electrically coupled to the interconnect may be extended into the side space for a distance sufficient to accommodate a redundant interconnect, extending the line end into the side space for the distance when available, and adding the redundant interconnect electrically coupled to the extended line end.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Inventors: LARS W. LIEBMANN, RASIT O. TOPALOGLU
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Publication number: 20170047252Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.Type: ApplicationFiled: June 7, 2016Publication date: February 16, 2017Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
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Publication number: 20170047418Abstract: A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.Type: ApplicationFiled: August 10, 2015Publication date: February 16, 2017Inventors: Su Chen Fan, Lars W. Liebmann, Ruilong Xie
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Publication number: 20170047254Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.Type: ApplicationFiled: June 7, 2016Publication date: February 16, 2017Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
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Patent number: 9570573Abstract: A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.Type: GrantFiled: August 10, 2015Date of Patent: February 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Su Chen Fan, Lars W. Liebmann, Ruilong Xie
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Publication number: 20160379929Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.Type: ApplicationFiled: May 12, 2016Publication date: December 29, 2016Inventors: Yannick Feurprier, Joe Lee, Lars W. Liebmann, Yann Mignot, Terry A. Spooner, Douglas M. Trickett, Mehmet Yilmaz
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Patent number: 9424386Abstract: Generating place and route abstracts, including: for each of a plurality of cells, generating a wire diagram; for each generated wire diagram, generating, in dependence upon a cell architecture layout, a cell architecture description; for each cell architecture description: generating, in dependence upon the wire diagrams and the cell architecture descriptions, a blockage map specifying locations where the placement of cells or routing structures is prohibited; and generating, in dependence upon the blockage maps and one or more design rules, a library exchange format (‘LEF’) abstract.Type: GrantFiled: November 20, 2014Date of Patent: August 23, 2016Assignee: International Business Machines CorporationInventors: Albert M. Chu, Lars W. Liebmann
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Patent number: 9418935Abstract: Integrated circuit structures formed using methods herein include a layer, and a material-filled line in the layer. The material-filled line includes a first linear item and a second linear item separated by a separation area of the layer. The first linear item has a first line end where the first linear item contacts the separation area. The second linear item has a second line end where the second linear item contacts the separation area. The first line end and the second line end include line end openings (filled with a material) that increase critical dimension uniformity of the first line end and the second line end.Type: GrantFiled: September 9, 2015Date of Patent: August 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Dongbing Shao, Lei L. Zhuang, Lars W. Liebmann, Lawrence A. Clevenger
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Patent number: 9397049Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.Type: GrantFiled: August 10, 2015Date of Patent: July 19, 2016Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
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Patent number: 9385078Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.Type: GrantFiled: March 9, 2016Date of Patent: July 5, 2016Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., TOKYO ELECTRON LIMITEDInventors: Yannick Feurprier, Joe Lee, Lars W. Liebmann, Yann Mignot, Terry A. Spooner, Douglas M. Trickett, Mehmet Yilmaz
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Patent number: 9373582Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.Type: GrantFiled: June 24, 2015Date of Patent: June 21, 2016Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., TOKYO ELECTRON LIMITEDInventors: Yannick Feurprier, Joe Lee, Lars W. Liebmann, Yann Mignot, Terry A. Spooner, Douglas M. Trickett, Mehmet Yilmaz
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Publication number: 20160147925Abstract: Generating place and route abstracts, including: for each of a plurality of cells, generating a wire diagram; for each generated wire diagram, generating, in dependence upon a cell architecture layout, a cell architecture description; for each cell architecture description: generating, in dependence upon the wire diagrams and the cell architecture descriptions, a blockage map specifying locations where the placement of cells or routing structures is prohibited; and generating, in dependence upon the blockage maps and one or more design rules, a library exchange format (‘LEF’) abstract.Type: ApplicationFiled: November 20, 2014Publication date: May 26, 2016Inventors: ALBERT M. CHU, LARS W. LIEBMANN