Abstract: The present invention discloses a method and a circuit for reducing switching ringing in a switching regulator. The switching regulator comprises two transistors, and the two transistors are never simultaneously OFF. A phase lock loop may be provided to fix the output signal frequency of a PWM control circuit to a set frequency.

Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.

Abstract: A control circuit provides a control signal for a constant on-time PWM switching converter to produce an output voltage, such that the converter operates with a constant on-time at a first state and operates with a variable on-time at a second state, so as to decrease the switching frequency and thereby the switching loss, to increase the efficiency of the converter, to improve the transient response, and to reduce the recovery time of the output voltage.

Abstract: A semiconductor device package comprises a first semiconductor die having a first source region, a first gate region, and a first drain region attached on a first leadframe, a second semiconductor die having a second source region, a second gate region, and a second drain region attached on a second leadframe, and several pins electrically connected to the leadframes and source and gate regions. The second leadframe is electrically connected to the first source region. The pins connected to the first leadframe and second source region are on a side of the package, and the pins connected to the first gate region, second leadframe, and second gate region are on another side of the package.

Abstract: A switching circuit uses multiple common-drain JFETs to serve as the low-side switches of the switching circuit, and each of the low-side JFET is coupled between a high-side switch and a power node. Since a JFET can endure high voltage at both drain side and source side, and has good heat dissipation capability at drain side, the drain of the low-side JFET is coupled to the power node to enhance the heat dissipation capability and accordingly, all the low-side JFETs are allowed to be packaged in a same package to reduce the PCB layout area.

Abstract: A control circuit and method are provided to generate a modulation signal to operate a power stage in a DC/DC PWM converter such that the DC/DC PWM converter is controlled to operate with high switching frequency in light load stead state, once load transient happens, it still operates with high switching frequency for good transient response, and in heavy load stead state, it is controlled to operate with low switching frequency for good efficiency.

Abstract: An overshoot suppression circuit comprises a switch for coupling to an output of a voltage regulation module and a voltage detector for detecting an output voltage at the output. When the load to the voltage regulation module changes from heavy to light to result in the output voltage higher than a threshold, the voltage detector turns on the switch to release energy from the output, and thereby the output voltage is suppressed to produce overshoot to damage the load coupled to the output.

Abstract: A switching circuit uses multiple common-drain JFETs to serve as the low-side switches of the switching circuit, and each of the low-side JFET is coupled between a high-side switch and a power node. Since a JFET can endure high voltage at both drain side and source side, and has good heat dissipation capability at drain side, the drain of the low-side JFET is coupled to the power node to enhance the heat dissipation capability and accordingly, all the low-side JFETs are allowed to be packaged in a same package to reduce the PCB layout area.

Abstract: For a DC-to-DC converter including a plurality of channels for converting an input voltage to an output voltage, a control circuit comprises a load transient detector to detect the output voltage to provide a quick response signal. In a load transient, the quick response signal triggers a quick transient response period to increase the operational frequency of the converter.

Abstract: Electronic circuits use low-cost depletion-mode JFET to serve as power switch. Since depletion-mode JFET has smaller conductive resistance and is majority carrier device, the energy loss is less when current flows through the depletion-mode JFET, and faster switching speed is obtained, thereby enhancing the efficiency of the electronic circuits.

Abstract: Electronic circuits use low-cost depletion-mode JFET to serve as power switch. Since depletion-mode JFET has smaller conductive resistance and is majority carrier device, the energy loss is less when current flows through the depletion-mode JFET, and faster switching speed is obtained, thereby enhancing the efficiency of the electronic circuits.

Abstract: A DC-to-DC converter comprises a sense circuit to sense the output voltage of the converter to generate a feedback signal, a transconductive amplifier to amplify a difference between the feedback signal and a threshold signal to generate a first current and to generate a second current in response to a load transient, a charging circuit connected with the first current to generate a charging voltage, a driver to compare the charging voltage with two reference signals to generate a pair of low-side and high-side driving signals, and a fast response circuit to compare a load transient signal corresponding to the second current with a third reference signal to generate a bypass signal to drive the output stage of the converter in the load transient.

Abstract: A two-step DC-to-DC converter comprises a first converter stage for converting a first voltage to a second voltage, and a second converter stage for converting the second voltage to an output voltage. The first converter stage uses a MOSFET or normally-off JFET to serve as a high-side switch, and the second converter stage comprises a multi-phase modulator using a normally-on JFET to serve as a high-side switch, thereby improving the efficiency of the two-step DC-to-DC converter.

Abstract: For a PWM controller chip in a voltage converter to switch a pair of high side and low side switches connected with a phase node therebetween, a circuit comprises a sense resistor connected between a multi-function pin on the PWM controller chip and the phase node, and an enable arrangement, a power sensing arrangement, and an over-current protection arrangement to detect the voltage on the multi-function pin for accomplishing enable function, power sensing, and over-current protection, respectively.

Abstract: To turn on a JFET, a two-stage turn-on current control is employed in a JFET driver circuit and a JFET driving method, by which a shortly pulsed high sourcing current is provided to turn on the JFET rapidly and efficiently, and a continuous low sourcing current is provided after the JFET turns on for reducing the power dissipation. After the JFET turns off, a negative charge pump is also employed to promise the JFET at a turn-off state. A special power sequence is further employed to ensure the JFET could be turned off during the power supply coupled to the JFET starts up.

Abstract: A fixed-frequency current mode converter comprises a power stage to produce an inductor current and an output voltage, an error amplifier to generate an error signal from the difference between the output voltage and a reference voltage varied with the inductor current, a comparator to compare the error signal with a ramp signal varied with the inductor current to generate a comparison signal, and a PWM generator to generate a PWM signal in response to a fixed-frequency clock and the comparison signal to drive the power stage. A second comparator is further comprised to compare the error signal with a second reference voltage varied with the inductor current, and generates a second comparison signal to reset the clock when the error signal is lower than the second reference voltage.

Abstract: A circuit and method for soft start of a system compare a feedback signal produced from an output voltage of the system with a ramp signal to generate a comparison signal, and enables the system once the comparison signal indicating the ramp signal reaches the feedback signal, such that the output voltage becomes active from a residual voltage toward a target level.

Abstract: A quick turn on apparatus and method for a NMOSFET switch are used to maintain the gate voltage of the NMOSFET switch non-zero but not enough to turn on the NMOSFET switch, such that the NMOSFET switch turns on more quickly when it is to be turned on. Seamless transition can be further achieved in a single pole double throw switching circuit by using the quick turn on apparatus and method.

Abstract: A real current sense apparatus for a DC-to-DC converter uses a current mirror composed by two JFETs to mirror the output current of the converter to generate a temperature-independent mirror current to further generate a current sense signal. Due to the temperature-independence of the mirror current, the current sense signal is also temperature-independent.

Abstract: A direct current voltage boosting/bucking device includes a direct current voltage boosting circuit and a low drop-out (LDO) linear voltage converting circuit. The direct current voltage boosting circuit boosts an input voltage so as to generate an output voltage higher than the input voltage. The LDO linear voltage converting circuit converts the output voltage into a load voltage that is to be provided to a load, and controls the direct current voltage boosting circuit in accordance with a feedback signal from the load such that the output voltage and the load voltage have a minimum drop-out voltage differential therebetween and such that current flow through the load is maintained at a determined level.