Patents by Inventor Lidija Sekaric
Lidija Sekaric has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9048258Abstract: Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.Type: GrantFiled: September 12, 2012Date of Patent: June 2, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Josephine B. Chang, Michael A. Guillorn, Amlan Majumdar, Lidija Sekaric
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Patent number: 9029132Abstract: A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.Type: GrantFiled: August 6, 2009Date of Patent: May 12, 2015Assignee: International Business Machines CorporationInventors: Marwan H. Khater, Tak H. Ning, Lidija Sekaric, Sufi Zafar
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Patent number: 8946068Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.Type: GrantFiled: August 15, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Devendra Sadana, Lidija Sekaric
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Patent number: 8940548Abstract: A method for sensing biomolecules in an electrolyte includes exposing a gate dielectric surface of a sensor comprising a silicon fin to the electrolyte, wherein the gate dielectric surface comprises a dielectric material and antibodies configured to bind with the biomolecules; applying a gate voltage to an electrode immersed in the electrolyte; and measuring a change in a drain current flowing in the silicon fin; and determining an amount of the biomolecules that are present in the electrolyte based on the change in the drain current.Type: GrantFiled: July 19, 2012Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Marwan H. Khater, Tak H. Ning, Lidija Sekaric, Sufi Zafar
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Patent number: 8884370Abstract: Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.Type: GrantFiled: April 27, 2012Date of Patent: November 11, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Amlan Majumdar, Lidija Sekaric
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Patent number: 8822318Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.Type: GrantFiled: June 21, 2013Date of Patent: September 2, 2014Assignee: Inernational Business Machines CorporationInventors: Ali Afzali-Ardakani, Damon Farmer, Lidija Sekaric
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Patent number: 8691675Abstract: A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.Type: GrantFiled: November 25, 2009Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Damon B. Farmer, Lidija Sekaric
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Publication number: 20130330918Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.Type: ApplicationFiled: August 15, 2013Publication date: December 12, 2013Applicant: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Devendra K. Sadana, Lidija Sekaric
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Publication number: 20130295754Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.Type: ApplicationFiled: June 21, 2013Publication date: November 7, 2013Inventors: Ali Afzali-Ardakani, Damon Farmer, Lidija Sekaric
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Publication number: 20130285126Abstract: Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.Type: ApplicationFiled: September 12, 2012Publication date: October 31, 2013Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Amlan Majumdar, Lidija Sekaric
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Publication number: 20130285142Abstract: Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Amlan Majumdar, Lidija Sekaric
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Patent number: 8546269Abstract: Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.Type: GrantFiled: April 3, 2009Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Tymon Barwicz, Guy Cohen, Lidija Sekaric, Jeffrey Sleight
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Patent number: 8513642Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.Type: GrantFiled: July 5, 2012Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Devendra K. Sadana, Lidija Sekaric
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Patent number: 8492802Abstract: An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.Type: GrantFiled: August 24, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Xiao Hu Liu, Lidija Sekaric
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Patent number: 8481413Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.Type: GrantFiled: March 11, 2010Date of Patent: July 9, 2013Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Damon B. Farmer, Lidija Sekaric
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Patent number: 8445948Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine-and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.Type: GrantFiled: September 20, 2010Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Sarunya Bangsaruntip, Guy Cohen, Sebastian U. Engelmann, Lidija Sekaric, Qingyun Yang, Ying Zhang
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Patent number: 8368125Abstract: An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.Type: GrantFiled: July 20, 2009Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Xiao Hu Liu, Lidija Sekaric
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Patent number: 8367492Abstract: An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.Type: GrantFiled: August 24, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Xiao Hu Liu, Lidija Sekaric
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Publication number: 20130015507Abstract: An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.Type: ApplicationFiled: August 24, 2012Publication date: January 17, 2013Applicant: International Business Machines CorporationInventors: Dureseti Chidambarrao, Xiao Hu Liu, Lidija Sekaric
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Patent number: 8354333Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.Type: GrantFiled: February 3, 2010Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Devendra K. Sadana, Lidija Sekaric