Abstract: An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

Abstract: A method for sensing biomolecules in an electrolyte includes exposing a gate dielectric surface of a sensor comprising a silicon fin to the electrolyte, wherein the gate dielectric surface comprises a dielectric material and antibodies configured to bind with the biomolecules; applying a gate voltage to an electrode immersed in the electrolyte; and measuring a change in a drain current flowing in the silicon fin; and determining an amount of the biomolecules that are present in the electrolyte based on the change in the drain current.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.

Abstract: A p-type semiconductor nanowire transistor is formed on the first semiconductor nanowire and an n-type semiconductor nanowire transistor is formed on the second semiconductor nanowire. The first and second semiconductor nanowires have a rectangular cross-sectional area with different width-to-height ratios. The type of semiconductor nanowires for each semiconductor nanowire transistor is selected such that top and bottom surfaces provide a greater on-current per unit width than sidewall surfaces in a semiconductor nanowire having a greater width-to-height ratio, while sidewall surfaces provide a greater on-current per unit width than top and bottom surfaces in the other semiconductor nanowire having a lesser width-to-height ratio. Different types of stress-generating material layers may be formed on the first and second semiconductor nanowire transistors to provide opposite types of stress, which may be employed to enhance the on-current of the first and second semiconductor nanowire transistors.

Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.

Abstract: In one exemplary embodiment, a method for fabricating a nanowire product comprising: providing a wafer having a buried oxide (BOX) upper layer in which a well is formed, the wafer further having a nanowire having ends resting on the BOX layer such that the nanowire forms a beam spanning said well; and forming a mask coating on an upper surface of the BOX layer leaving an uncoated window over a center part of said beam over said well and also forming a mask coating around beam intermediate ends between each end of a beam center part and a side wall of said well.

Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.

Abstract: A semiconductor nanowire is coated with a chemical coating layer that comprises a functional material which modulates the quantity of free charge carriers within the semiconductor nanowire. The outer surface of the chemical coating layer includes a chemical group that facilitates bonding with molecules to be detected through electrostatic forces. The bonding between the chemical coating layer and the molecules alters the electrical charge distribution in the chemical coating layer, which alters the amount of the free charge carriers and the conductivity in the semiconductor nanowire. The coated semiconductor nanowire may be employed as a chemical sensor for the type of chemicals that bonds with the functional material in the chemical coating layer. Detection of such chemicals may indicate pH of a solution, a vapor pressure of a reactive material in gas phase, and/or a concentration of a molecule in a solution.

Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.

Abstract: In one embodiment, a semiconductor nanowire having a monotonically increasing width with distance from a middle portion toward adjoining semiconductor pads is provided. A semiconductor link portion having tapered end portions is lithographically patterned. During the thinning process that forms a semiconductor nanowire, the taper at the end portions of the semiconductor nanowire provides enhanced mechanical strength to prevent structural buckling or bending. In another embodiment, a semiconductor nanowire having bulge portions are formed by preventing the thinning of a semiconductor link portion at pre-selected positions. The bulge portions having a greater width than a middle portion of the semiconductor nanowire provides enhanced mechanical strength during thinning of the semiconductor link portion so that structural damage to the semiconductor nanowire is avoided during thinning.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.

Abstract: A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.

Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.

Abstract: A semiconductor nanowire is coated with a chemical coating layer that selectively attaches to the semiconductor material and which forms a dye in a chemical reaction. The dye layer comprises a material that absorbs electromagnetic radiation. A portion of the absorbed energy induces electronic excitation in the chemical coating layer from which additional free charge carriers are temporarily donated into the semiconductor nanowire. Thus, the conductivity of the semiconductor nanowire increases upon illumination on the dye layer. The semiconductor nanowire, and the resulting dye layer collective operate as a detector for electromagnetic radiation.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.