Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: Disclosed herein are glass compositions that present several advantages over glasses and other materials currently used for redistribution layers for RF, interposers, and similar applications. The glasses disclosed herein are low cost, flat glasses that have high throughput for the laser damage and etching process used to create through glass vias (TGV). TGV generated using the silicate glasses and processes described herein have large waist diameters (Dw), which is a desirable feature with respect to producing glass articles such as interposers.

Abstract: The invention provides a Probiotic microcapsule and a preparation method thereof, relating to the technical field of Probiotic products. The method includes the following steps: (a) preparing a capsule core containing Probiotics: mixing the capsule core materials including Probiotic powder, microcrystalline cellulose and starch, then adding a hydroxypropyl methylcellulose solution thereinto, while mixing evenly, making the obtained mixture materials into spherical particulate capsule cores by the extrusion spherization method; (b) coating by atomization: coating the microcapsule cores with a coating material solution in a single layer or multiple layers by atomization, getting core-shell microcapsules. The Probiotic microcapsules prepared by the present invention have a large encapsulation, uniform microcapsule particles, controllable particle size, storage-resistance, targetability to intestinal tracts, resistance to gastric acids and high temperature stability.

Abstract: The present technology can include a semiconductor device assembly comprising an RDL with a top surface and a side surface intersecting the top surface. The assembly can further comprise a semiconductor device coupled to the top surfaces, and a mold material encasing the semiconductor device (when included) and directly coupled to at least a portion of the top surface and the side surface of the RDL. In other embodiments, the assembly can comprise an RDL with a top surface, a bottom surface opposite thereto, and a sloped side surface extending between the top surface and the bottom surface. The assembly similarly can further comprise a semiconductor device coupled to the top surface, and a mold material encasing the semiconductor device and directly coupled to at least a portion of the top surface and the side surface of the RDL.

Abstract: A display panel and a display device are disclosed, the display panel comprises: a base substrate; and pixel circuits in an array, the display panel comprises a light transmittance region and a display region around the light transmittance region, the pixel circuits are disposed in the display region, a gate line of each row of m rows of pixel circuits is divided into a first gate line portion and a second gate line portion which are connected through an auxiliary gate line, a data line of each column of n columns of pixel circuits is divided into a first data line portion and a second data line portion which are connected through an auxiliary data line.

Abstract: A display substrate and a display device are provided. Sub-pixels in the display substrate include a first electrode, a light emitting layer and a second electrode which are sequentially stacked; each second electrode includes a main body electrode and a connecting electrode. The sub-pixels include first color sub-pixels and second color sub-pixels, the main body electrode of a same first color sub-pixel is a continuous electrode. The sub-pixels include sub-pixel pairs, each sub-pixel pair includes a first pixel block and a second pixel block, a shape of the second electrode of the second pixel block is different from that of the second electrode of the first pixel block.

Abstract: A computer-implemented method includes preprocessing, by a compiler, a plurality of macros in a computer program. Preprocessing a macro includes identifying a compile time condition associated with the macro. Preprocessing the macro further includes determining a current value of the compile time condition at the time of compiling a computer instruction and a previous value of the compile time condition. Preprocessing the macro further includes determining a set of computer instructions enclosed by the macro. The method further includes storing a macro information record that includes the compile time condition, the current value and the previous value of the compile time condition, and an identification of the set of computer instructions enclosed by the macro.

Abstract: Embodiments disclosed herein include through silicon waveguides and methods of forming such waveguides. In an embodiment, a through silicon waveguide comprises a substrate, where the substrate comprises silicon. In an embodiment, a waveguide is provided through the substrate. In an embodiment, the waveguide comprises a waveguide structure. and a cladding around the waveguide structure.

Abstract: Embodiments disclosed herein include a photonics module and methods of forming photonics modules. In an embodiment, the photonics module comprises a waveguide, and a modulator adjacent to the waveguide. In an embodiment, the modulator comprises a PN junction with a P-doped region and an N-doped region, where the PN junction is vertically oriented so that the P-doped region is over the N-doped region.

Abstract: A manufacturing method of a tiling electronic device includes the following steps. A first electronic panel is provided. The first electronic panel includes multiple first bumps and multiple first conducting lines, and the first bumps and the first conducting lines are disposed on a side surface of the first electronic panel. A second electronic panel is provided. The second electronic panel includes multiple second bumps and multiple second conducting lines, and the second bumps and the second conducting lines are disposed on a side surface of the second electronic panel. The first electronic panel and the second electronic panel are coupled through the first bumps and the second bumps. Multiple conducting elements are formed, so that the first conducting lines are electrically connected with the second conducting lines through the conducting elements after the first electronic panel and the second electronic panel are coupled.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An optical imaging lens includes first, second, third, fourth, fifth, and sixth lens elements sequentially along an optical axis from an object side to an image side. Each of the first to the sixth lens elements includes an object-side surface facing the object side and allowing imaging rays to pass through and an image-side surface facing the image side and allowing the imaging rays to pass through. The optical imaging lens satisfies conditions of Gallmax/Fno?3.600 millimeters, EFL/ImgH?3.200, and Gallmax/Tavg?3.300; here, Gallmax represents a largest air gap along the optical axis between the first lens element and an image plane, Fno, EFL, and ImgH respectively represent an F-number, an effective focal length, and an image height of the optical imaging lens, and Tavg represents an average lens element thickness of all of the lens elements along the optical axis from the object side to the image plane.

Abstract: A compound of Formula (I), or a pharmaceutically acceptable salt thereof, is provided that has been shown to be useful for treating a PRC2-mediated disease or disorder: wherein R1, R2, R3, R4, R5, and n are as defined herein.

Abstract: A liquid-cooling device includes multiple water blocks and at least one connection tube. Each of the water blocks has a water incoming end, a water outgoing end and a water-receiving space in communication with the water incoming end and the water outgoing end. The connection tube is disposed between each two water blocks. Two ends of the connection tube are respectively connected with the water incoming end of one of the two water blocks and the water outgoing end of the other water block, whereby the water-receiving spaces of the two water blocks communicate with each other via the connection tube. The connection tube has at least one bellows section between two ends of the connection tube. The liquid-cooling device solves the problems of the conventional liquid-cooling device that when the water block is welded, thermal deformation is produced to cause tolerance and the manufacturing cost is higher.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, where the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.

Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.

Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Abstract: A data migration method and an apparatus are provided. The method is as follows: sending, by a first storage system, a location update request to a location server, where the location update request is used to indicate the location server to update location information of a first bucket from being located in a second storage system to being located in the first storage system; migrating data in a first bucket from the second storage system; receiving a data access request, where the data access request is used to access the data in the first bucket; and determining based on a type of the data access request and a migration status of the data, that the first storage system or the second storage system processes the data access request.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.