Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.

Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.

Abstract: A multi-resistance-state spintronic device, including: a top electrode and a bottom electrode respectively connected to a read-write circuit; and a magnetic tunnel junction between two electrodes. The magnetic tunnel junction includes from top to bottom: a ferromagnetic reference layer, a barrier tunneling layer, a ferromagnetic free layer, and a spin-orbit coupling layer. Nucleation centers are provided at two ends of the ferromagnetic free layer to generate a magnetic domain wall; the spin-orbit coupling layer is connected to the bottom electrode, and when a write pulse is applied, an electron spin current is generated and drives the magnetic domain wall through a spin-orbit torque to move; a plurality of local magnetic domain wall pinning centers are provided at an interface between the spin-orbit coupling layer and the ferromagnetic free layer to enhance a strength of a DM interaction constant between interfaces.

Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).

Abstract: The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.

Abstract: A light guide module is provided, which includes a circuit board, one or more light-emitting elements, a light guide plate, a first reflective layer and a second reflective layer. The one or more light-emitting elements are disposed on the circuit board. The light guide plate is located on the circuit board, in which the light guide plate has a thick portion and a thin portion connected to the thick portion, and the thin portion is located over the one or more light-emitting elements, and a side surface of the thick portion adjacent to the thin portion is laterally adjacent to the one or more light-emitting elements. The first reflective layer covers a side surface of the thick portion away from the thin portion. The second reflective layer covers an upper surface of the thick portion and an upper surface of the thin portion.

Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.

Abstract: A light source module includes a first light source and a second light source. The first light source is configured for emitting a first light having a first wavelength, and the first light includes a first part and a second part. The second light source is configured for emitting a second light having a second wavelength. The second light source includes a first wavelength conversion layer, and the first wavelength conversion layer is configured for converting the first light into the second light. One of the first part and the second part is incident to the first wavelength conversion layer, and the other of the first part and the second part is not incident to the first wavelength conversion layer.

Abstract: Disclosed in the present invention is an optimized cell transplant. The optimized cell transplant is formed by performing gene induction and modification on a mesenchymal stem cell in the form of a small molecule and protein composition. The expression levels of CD200 gene, Galectin-9 gene and VISTA gene can be increased synchronously after cell culture. Vector virus infection and plasmid transfection are not required in the cell preparation process, so that high biological safety and great clinical application value of cells are achieved.

Abstract: A system and method of docking an information handling system to an intelligent wireless fan dock comprising a docking sensor to detect a docking event, a wireless module to establish a wireless link of the intelligent wireless fan dock with the docked information handling system upon detection of a docking event and to receive a dynamic fan speed request command to adjust extended fan cooling airflow from fan dock control system operating at the docked information handling system, where the fan dock control system has determined that the docked information handling system and the intelligent wireless fan dock pairing enables an increased performance mode and altered power draw limitations for the docked information handling system relative to the information handling system in an undocked state, and increasing the extended fan cooling airflow of a cooling fan based on the dynamic fan speed request command from the docked information handling system.

Abstract: A reasonable millisecond time control method for excavation blasting of a tunnel is provided, and includes: acquiring physical mechanical parameters to establish a millisecond blasting model, and designing four dimensions blasting parameters of explosive quantity, hole number, inter-hole millisecond and inter-row millisecond; simulating, based on the millisecond blasting model, a blasting process of an explosive package using blasting parameters to obtain a blasting vibration curve; obtaining single-hole blasting vibration waveforms, solving a vibration synthesis curve through a vibration synthesis theory; comparing the vibration synthesis curve with the blasting vibration curve to obtain a coupling relationship of blasting parameters; determining a target group of explosive quantity and hole numbers, determining a target millisecond through the coupling relationship of blasting parameters, and relating a millisecond blasting control strategy to control, and it is used for tunneling project to reduce cut blas

Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.

Abstract: A method, network node and wireless device (WD) for collision handling, uplink control channel information (UCI) multiplexing and repetition for transport block (TB) transmission on a multi-slot physical uplink shared channel (PUSCH) are disclosed. According to one aspect, a method in a WD includes configuring a multi-slot physical uplink shared channel (PUSCH) by overlapping a multi-slot PUSCH with at least one of another PUSCH and/or a physical uplink control channel (PUCCH).

Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.

Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.

Abstract: A data migration method and an apparatus are provided. The method is as follows: sending, by a first storage system, a location update request to a location server, where the location update request is used to indicate the location server to update location information of a first bucket from being located in a second storage system to being located in the first storage system; migrating data in a first bucket from the second storage system; receiving a data access request, where the data access request is used to access the data in the first bucket; and determining based on a type of the data access request and a migration status of the data, that the first storage system or the second storage system processes the data access request.

Abstract: A transparent electronic device includes an organic film, an amorphous transparent oxycarbide layer, and a matrix layer. The organic film includes a polymer containing carboxyl groups (—COOH). The amorphous transparent oxycarbide layer is disposed on the organic film and consists of a metal element, carbon element, oxygen element and an additional element. The metal element is selected from molybdenum (Mo), indium (In), tin (Sn), zinc (Zn), cadmium (Cd) and a combination thereof. An atomic number percentage of the additional element is equal to or greater than 0%, and is less than the least of an atomic number percentage of the metal element, an atomic number percentage of the oxygen element and an atomic number percentage of the carbon element. The matrix layer is disposed on the amorphous transparent oxycarbide layer. A manufacturing method of a transparent electronic device is also provided.