Abstract: A method and a device for displaying a motion path of robot and a robot. The method for displaying a motion path of the robot includes acquiring a current motion path of the robot, recognizing the motion path to determine a type of the motion path, determining, according to the type of the motion path, a display manner corresponding to the type of the motion path, and displaying the motion path on an electronic map in the determined display manner.

Abstract: A transistor device is disclosed. The transistor device includes: a semiconductor body; a source conductor on top of the semiconductor body; a source clip on top of the source conductor and electrically connected to the source conductor; a first active device region arranged in the semiconductor body, covered by the source conductor and the source clip, and including at least one device cell; and a second active device region arranged in the semiconductor body, covered by regions of the source conductor that are not covered by the source clip, and including at least one device cell. The first active device region has a first area specific on-resistance and the second active device region has a second area specific on-resistance, the second area specific on-resistance being greater than the first area specific on-resistance.

Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

Abstract: A room-temperature semiconductor maser, including a first matching network, a second matching network, a heterojunction-containing transistor, and a resonant network. The output end of the first matching network is connected to the drain of the heterojunction-containing transistor. The input end of the second matching network is connected to the source of the heterojunction-containing transistor. The gate of the heterojunction-containing transistor is connected to the resonant network. The pumped microwaves are fed into the input end of the first matching network.

Abstract: The present invention relates to the field of reliability-based structural design optimization, and provides an integration method for accurate modeling and analysis and reliability-based design optimization of variable stiffness composite plate and shell structures. In this method, the first-order reliability method, two-point adaptive nonlinear approximation and second-order reliability method are applied into the efficient reliability-based design optimization of variable stiffness composite plate and shell structures. The fiber placement path of variable stiffness composite plate and shell structures is accurately modeled by non-uniform rational B-spline function. Isogeometric analysis is utilized for the variable stiffness composite plate and shell structures, including conducting linear buckling analysis on the variable stiffness composite plate and shell structures based on the isogeometric analysis method and deriving analytical sensitivity of design and random variables on the structural response.

Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.

Abstract: A method and a device for displaying a motion path of robot and a robot. The method for displaying a motion path of the robot includes acquiring a current motion path of the robot, recognizing the motion path to determine a type of the motion path, determining, according to the type of the motion path, a display manner corresponding to the type of the motion path, and displaying the motion path on an electronic map in the determined display manner.

Abstract: The present disclosure provides a method of treating seizure in a subject having aberrant alkaline phosphatase activities, comprising administering a therapeutically effective amount of at least one recombinant alkaline phosphatase to the subject.

Abstract: A transistor device is disclosed. The transistor device includes: a semiconductor body; a source conductor on top of the semiconductor body; a source clip on top of the source conductor and electrically connected to the source conductor; a first active device region arranged in the semiconductor body, covered by the source conductor and the source clip, and including at least one device cell; and a second active device region arranged in the semiconductor body, covered by regions of the source conductor that are not covered by the source clip, and including at least one device cell. The first active device region has a first area specific on-resistance and the second active device region has a second area specific on-resistance, the second area specific on-resistance being greater than the first area specific on-resistance.

Abstract: The present disclosure provides a method of treating seizure in a subject having aberrant alkaline phosphatase activities, comprising administering a therapeutically effective amount of at least one recombinant alkaline phosphatase to the subject.

Abstract: A package which comprises an electrically conductive chip carrier, a first chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, a second chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, wherein the first chip and the second chip are connected to form a half bridge having inlet terminals and an outlet terminal, and a clip having three connection sections connecting the second connection terminal of the first chip with the first connection terminal of the second chip and with the outlet terminal of the half bridge.

Abstract: The present invention relates to the field of reliability-based structural design optimization, and provides an integration method for accurate modeling and analysis and reliability-based design optimization of variable stiffness composite plate and shell structures. In this method, the first-order reliability method, two-point adaptive nonlinear approximation and second-order reliability method are applied into the efficient reliability-based design optimization of variable stiffness composite plate and shell structures. The fiber placement path of variable stiffness composite plate and shell structures is accurately modeled by non-uniform rational B-spline function. Isogeometric analysis is utilized for the variable stiffness composite plate and shell structures, including conducting linear buckling analysis on the variable stiffness composite plate and shell structures based on the isogeometric analysis method and deriving analytical sensitivity of design and random variables on the structural response.

Abstract: A package which comprises an electrically conductive chip carrier, a first chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, a second chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, wherein the first chip and the second chip are connected to form a half bridge having inlet terminals and an outlet terminal, and a clip having three connection sections connecting the second connection terminal of the first chip with the first connection terminal of the second chip and with the outlet terminal of the half bridge.

Abstract: An interconnect module includes a metal clip having a first end section, a second end section and a middle section extending between the first and the second end sections. The first end section is configured for external attachment to a bare semiconductor die or packaged semiconductor die attached to a carrier or to a metal region of the carrier. The second end section is configured for external attachment to a different metal region of the carrier or to a different semiconductor die or packaged semiconductor die attached to the carrier. The module further includes a magnetic field sensor secured to the metal clip. The magnetic field sensor is operable to sense a magnetic field produced by current flowing through the metal clip. The interconnect module can be used to form a direct electrical connection between components and/or metal regions of a carrier to which the module is attached.

Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.

Abstract: The present disclosure provides a method of treating seizure in a subject having aberrant alkaline phosphatase activities, comprising administering a therapeutically effective amount of at least one recombinant alkaline phosphatase to the subject.

Abstract: A integrated power module with integrated power electronic circuitry and logic circuitry includes an embedded power semiconductor module including one or more power semiconductor dies embedded in a dielectric material, a multi-layer logic printed circuit board with one or more logic dies mounted to a surface of the logic printed circuit board, and a flexible connection integrally formed between the embedded power semiconductor module and the logic printed circuit board. The flexible connection mechanically connects the embedded power semiconductor module to the logic printed circuit board and provides an electrical pathway between the embedded power semiconductor module and the logic printed circuit board. A method of manufacturing the integrated power module is also provided.

Abstract: A semiconductor package includes a semiconductor die attached to a substrate and a magnetic field sensor included as part of the same semiconductor package as the semiconductor die and positioned in close proximity to a current pathway of the semiconductor die so that the magnetic field sensor can sense a magnetic field produced by current flowing in the current pathway. The magnetic field sensor includes a first magnetic field sensing component galvanically isolated from the current pathway and positioned so that a magnetic field produced by current flowing in the current pathway impinges on the first magnetic field sensing component in a first direction. The magnetic field sensor also includes a second magnetic field sensing component galvanically isolated from the current pathway and positioned so that the magnetic field impinges on the second magnetic field sensing component in a second direction different than the first direction.

Abstract: A power semiconductor package includes a substrate having a plurality of metal leads, a power semiconductor die attached to a first one of the leads and a magnetic field sensor integrated in the same power semiconductor package as the power semiconductor die and positioned in close proximity to a current pathway of the power semiconductor die. The magnetic field sensor is operable to generate a signal in response to a magnetic field produced by current flowing in the current pathway, the magnitude of the signal being proportional to the amount of current flowing in the current pathway.

Abstract: A power semiconductor package includes a substrate having a plurality of metal leads, a power semiconductor die attached to a first one of the leads and a magnetic field sensor integrated in the same power semiconductor package as the power semiconductor die and positioned in close proximity to a current pathway of the power semiconductor die. The magnetic field sensor is operable to generate a signal in response to a magnetic field produced by current flowing in the current pathway, the magnitude of the signal being proportional to the amount of current flowing in the current pathway.