Patents by Inventor Ljubisa Dragoljub Stevanovic
Ljubisa Dragoljub Stevanovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10559553Abstract: A power module includes a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side.Type: GrantFiled: April 9, 2019Date of Patent: February 11, 2020Assignee: General Electric CompanyInventors: Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic
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Patent number: 10403711Abstract: In one embodiment, a method of manufacturing a silicon-carbide (SiC) device includes receiving a selection of a specific terrestrial cosmic ray (TCR) rating at a specific applied voltage, determining a breakdown voltage for the SiC device based at least on the specific TCR rating at the specific applied voltage, determining drift layer design parameters based at least on the breakdown voltage. The drift layer design parameters include doping concentration and thickness of the drift layer. The method also includes fabricating the SiC device having a drift layer with the determined drift layer design parameters. The SiC device has the specific TCR rating at the specific applied voltage.Type: GrantFiled: October 17, 2016Date of Patent: September 3, 2019Assignee: GENERAL ELECTRIC COMPANYInventors: Alexander Viktorovich Bolotnikov, Ljubisa Dragoljub Stevanovic, Peter Almern Losee
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Patent number: 10404186Abstract: A power module includes an input bus, a switching device, and an output bus. The input bus includes a first coating of a high permeability magnetic conductive material and is configured to receive input direct current (DC) electrical power from an electrical power source. The switching device is electrically coupled to the first input bus, and is configured to selectively connect and disconnect to facilitate converting the input DC electrical power into output alternating current (AC) electrical power. The output bus includes a second coating of the high permeability magnetic conductive material, and is electrically coupled to the first switching device. The output bus is configured to supply the output AC electrical power to an electrical load.Type: GrantFiled: October 27, 2016Date of Patent: September 3, 2019Assignee: GENERAL ELECTRIC COMPANYInventors: Michael Joseph Schutten, Fengfeng Tao, Maja Harfman-Todorovic, Ravisekhar Nadimpalli Raju, Philip Michael Cioffi, Ljubisa Dragoljub Stevanovic
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Publication number: 20190237440Abstract: A power module may include a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side.Type: ApplicationFiled: April 9, 2019Publication date: August 1, 2019Inventors: Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic
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Patent number: 10347608Abstract: A power module includes a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side.Type: GrantFiled: May 25, 2017Date of Patent: July 9, 2019Assignee: GENERAL ELECTRIC COMPANYInventors: Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic
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Patent number: 10186509Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.Type: GrantFiled: October 25, 2016Date of Patent: January 22, 2019Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, James Jay McMahon, Ljubisa Dragoljub Stevanovic
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Publication number: 20180212512Abstract: Systems and methods for providing automatic short circuit protection in an electrical system via a switching device. In some embodiments, the switching device includes a switching transistor that selectively switches between an open position and a closed position based at least in part on a switching control signal, for example, to facilitate converting electrical power with first electrical characteristics output into electrical power with the second electrical characteristics.Type: ApplicationFiled: January 20, 2017Publication date: July 26, 2018Inventors: Ravisekhar Nadimpalli Raju, Ramanujam Ramabhadran, Ljubisa Dragoljub Stevanovic, William George Earls
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Patent number: 10033298Abstract: Systems and methods for providing automatic short circuit protection in an electrical system via a switching device. In some embodiments, the switching device includes a switching transistor that selectively switches between an open position and a closed position based at least in part on a switching control signal, for example, to facilitate converting electrical power with first electrical characteristics output into electrical power with the second electrical characteristics.Type: GrantFiled: January 20, 2017Date of Patent: July 24, 2018Assignee: GENERAL ELECTRIC COMPANYInventors: Ravisekhar Nadimpalli Raju, Ramanujam Ramabhadran, Ljubisa Dragoljub Stevanovic, William George Earls
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Patent number: 9972569Abstract: A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality of power semiconductor switches arranged thereon, and at least one second conductive substrate electrically coupled to the first conductive substrate. A first terminal is electrically coupled to the first conductive substrate. The power module also includes a second substrate including a third conductive substrate having a second plurality of power semiconductor switches arranged thereon, and at least one fourth conductive substrate electrically coupled to the third conductive substrate. The third conductive substrate is electrically coupled to the second conductive substrate. A second terminal is electrically coupled to the fourth conductive substrate.Type: GrantFiled: April 7, 2017Date of Patent: May 15, 2018Assignee: GENERAL ELECTRIC COMPANYInventors: Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic
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Publication number: 20180123476Abstract: A power module includes an input bus, a switching device, and an output bus. The input bus includes a first coating of a high permeability magnetic conductive material and is configured to receive input direct current (DC) electrical power from an electrical power source. The switching device is electrically coupled to the first input bus, and is configured to selectively connect and disconnect to facilitate converting the input DC electrical power into output alternating current (AC) electrical power. The output bus includes a second coating of the high permeability magnetic conductive material, and is electrically coupled to the first switching device. The output bus is configured to supply the output AC electrical power to an electrical load.Type: ApplicationFiled: October 27, 2016Publication date: May 3, 2018Inventors: Michael Joseph Schutten, Fengfeng Tao, Maja Harfman-Todorovic, Ravisekhar Nadimpalli Raju, Philip Michael Cioffi, Ljubisa Dragoljub Stevanovic
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Patent number: 9899512Abstract: Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×1014 cm?2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.Type: GrantFiled: February 24, 2016Date of Patent: February 20, 2018Assignee: GENERAL ELECTRIC COMPANYInventors: Peter Almern Losee, Ljubisa Dragoljub Stevanovic, Gregory Thomas Dunne, Alexander Viktorovich Bolotnikov
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Patent number: 9893646Abstract: A method and system for a power module device is provided. The device includes a base, a circuit board including a plurality of gated switches formed of a semiconductor material, and an electrical bus member configured to connect to a voltage source having a first polarity. The bus member includes a length that is substantially greater than a width of the bus member and the width is substantially greater than a thickness of the bus member. The power module device also includes a second bus member configured to connect to a voltage source having a second polarity. The second bus member is positioned in a nested face-to-face configuration with respect to the first bus member. The power module device further includes a layer of electrical insulation positioned between the first bus member and the second bus member.Type: GrantFiled: September 30, 2015Date of Patent: February 13, 2018Assignee: General Electric CompanyInventors: Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic
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Publication number: 20170345799Abstract: A power module may include a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side.Type: ApplicationFiled: May 25, 2017Publication date: November 30, 2017Inventors: Brian Lynn ROWDEN, Ljubisa Dragoljub STEVANOVIC
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Publication number: 20170294434Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.Type: ApplicationFiled: October 25, 2016Publication date: October 12, 2017Inventors: Avinash Srikrishnan KASHYAP, Peter Micah SANDVIK, James Jay MCMAHON, Ljubisa Dragoljub STEVANOVIC
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Publication number: 20170294373Abstract: A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality of power semiconductor switches arranged thereon, and at least one second conductive substrate electrically coupled to the first conductive substrate. A first terminal is electrically coupled to the first conductive substrate. The power module also includes a second substrate including a third conductive substrate having a second plurality of power semiconductor switches arranged thereon, and at least one fourth conductive substrate electrically coupled to the third conductive substrate. The third conductive substrate is electrically coupled to the second conductive substrate. A second terminal is electrically coupled to the fourth conductive substrate.Type: ApplicationFiled: April 7, 2017Publication date: October 12, 2017Inventors: Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic
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Publication number: 20170243935Abstract: In one embodiment, a method of manufacturing a silicon-carbide (SiC) device includes receiving a selection of a specific terrestrial cosmic ray (TCR) rating at a specific applied voltage, determining a breakdown voltage for the SiC device based at least on the specific TCR rating at the specific applied voltage, determining drift layer design parameters based at least on the breakdown voltage. The drift layer design parameters include doping concentration and thickness of the drift layer. The method also includes fabricating the SiC device having a drift layer with the determined drift layer design parameters. The SiC device has the specific TCR rating at the specific applied voltage.Type: ApplicationFiled: October 17, 2016Publication date: August 24, 2017Inventors: Alexander Viktorovich Bolotnikov, Ljubisa Dragoljub Stevanovic, Peter Almern Losee
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Publication number: 20170243970Abstract: Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×1014 cm?2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.Type: ApplicationFiled: February 24, 2016Publication date: August 24, 2017Inventors: Peter Almern Losee, Ljubisa Dragoljub Stevanovic, Greg Thomas Dunne, Alexander Viktorovich Bolotnikov
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Publication number: 20170093302Abstract: A method and system for a power module device is provided. The device includes a base, a circuit board including a plurality of gated switches formed of a semiconductor material, and an electrical bus member configured to connect to a voltage source having a first polarity. The bus member includes a length that is substantially greater than a width of the bus member and the width is substantially greater than a thickness of the bus member. The power module device also includes a second bus member configured to connect to a voltage source having a second polarity. The second bus member is positioned in a nested face-to-face configuration with respect to the first bus member. The power module device further includes a layer of electrical insulation positioned between the first bus member and the second bus member.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic
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Patent number: 9508841Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.Type: GrantFiled: August 1, 2013Date of Patent: November 29, 2016Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, James Jay McMahon, Ljubisa Dragoljub Stevanovic
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Patent number: 9406762Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.Type: GrantFiled: May 15, 2013Date of Patent: August 2, 2016Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Matocha, Richard Joseph Saia, Zachary Matthew Stum, Ljubisa Dragoljub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer