Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: A plurality of holes are formed extending vertically in a first dielectric deck that includes interleaved a plurality of first sacrificial layers and a plurality of first dielectric layers over a substrate. A plurality of sacrificial structures are formed in the holes. A second dielectric deck is formed having interleaved a plurality of second sacrificial layers and a plurality of second dielectric layers over the first dielectric deck. A slit opening is formed extending in the second dielectric deck, the slit opening aligned with and over the sacrificial source contact structures. The sacrificial structures are removed through the slit openings such that the slit opening is in contact with the holes to form a slit structure. A plurality of conductor layers are formed in the first and second dielectric decks through the slit structure, forming a memory stack. A source contact structure is formed in the slit structure.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: A call to action processor receives an entity datapoint containing data related to an entity, a campaign objective datapoint containing data associated with a campaign objective, at least one definite script element based on the campaign objective, and entity metadata containing data associated with the entity. The call to action further performs generating at least one variable script element based on the entity metadata, presenting to a device the at least one definite script element the at least one variable script element.

Abstract: Molten carbonate fuel cell configurations are provided that allow for introduction of an anode input gas flow on a side of the fuel cell that is adjacent to the entry side for the cathode input gas flow while allowing the anode and cathode to operate under co-current flow and/or counter-current flow conditions. It has been discovered that improved flow properties can be achieved within the anode or cathode during co-current flow or counter-current flow operation by diverting the input flow for the anode or cathode into an extended edge seal region (in an extended edge seal chamber) adjacent to the active area of the anode or cathode, and then using a baffle to provide sufficient pressure drop for even flow distribution of the anode input flow across the anode or cathode input flow across the cathode.

Abstract: A display device is provided, including: a back plate; a plastic frame connected to the back plate; a backlight module; a privacy film on a light emitting side of the backlight module; and a dimming sheet on a side of privacy film away from the back plate, wherein the dimming sheet is configured to be capable of adjusting a viewing angle of the display device. The plastic frame includes a first surface and a side end face, the first surface is a surface of the plastic frame close to the dimming sheet, the side end face is a side face of the plastic frame close to the dimming sheet, the plastic frame further includes a chamfered portion at a transition position between the side end face and the first surface, and the chamfered portion has a rough surface that is configured for diffracting the light incident on the chamfered portion.

Abstract: Systems and methods are provided for performing both reforming and partial oxidation as part of the reaction step of a reaction cycle in a cyclic reaction environment such as a reverse flow reaction environment, where heat is provided by direct heating during a regeneration step. In some aspects, performing a combination of reforming and partial oxidation can allow for higher conversion of hydrocarbons than reforming alone while reducing or minimizing the peak temperatures within the cyclic reaction environment. In some aspects, performing both reforming and partial oxidation can also allow for an improved molar ratio of H2 to CO in the resulting effluent from the conversion reaction (relative to partial oxidation) while still maintaining high total conversion.

Abstract: An array substrate and a display panel. The array substrate provided in the embodiments of the present application includes: a base including a flat portion and a recess portion so that the base includes a concave hole corresponding to the bending area; a semiconductor component layer provided on the base and including a plurality of interlayer insulation layers and a plurality of metal layers, the interlayer insulation layers being not aligned horizontally in the peripheral area and the wire switching area to form a stepped hole including a first hole and a second hole, wherein a third metal layer of the metal layers extends along a sidewall and a bottom of the stepped hole and is electrically connected to a first metal layer of the metal layers.

Abstract: The application discloses an array substrate and a mother-board for array substrates. The array substrate includes a display area and a non-display area on a periphery of the display area. The non-display area is provided with an interface area. The array substrate includes: multiple signal lines extending in the display area and leading to the non-display area; multiple pads located in the interface Area, and each of the multiple pads is connected to a corresponding one of the multiple signal lines; and a short-circuiting component located in the non-display area, wherein the short-circuiting component is connected with the multiple pads, the multiple signal lines connected with the pads are short-circuited, and the short-circuiting component includes a patterned first metal structure. The array substrate according to embodiments of the present application can avoid problems caused by static electricity, such as, electrostatic damage or product defects.

Abstract: A display and a display panel are provided. An additional VDD wire is arranged in an irregular-shaped region. The VDD wire is connected to a pixel arranged in the irregular-shaped region through a plurality of connection wires, such that the display may have a narrow side edge, and at the same time, a difference between impedances of the irregular-shaped region and a regular-shaped display region may not be large, and a display region may not be split.

Abstract: A display substrate and manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, and a shift register unit and a first clock signal line that are on the base substrate, the first clock signal line extends along a first direction on the base substrate and is configured to provide a first clock signal to the shift register unit, the shift register unit includes an input circuit, an output circuit, a first control circuit and an output control circuit, and the input circuit includes an input transistor, an active layer of the input transistor is in a strip shape extending along a second direction, and the second direction is different from the first direction.

Abstract: Provided is a chimeric antigen receptor, comprising an antigen binding region, a transmembrane domain and an intracellular signaling region. The antigen binding region comprises an antibody specifically targeting CD7, and the intracellular signaling region consists of a co-stimulatory domain, a primary signal transduction domain, and a ?C chain or intracellular region thereof. Also provided are an engineered immune cell comprising the chimeric antigen receptor and a pharmaceutical composition thereof, and use of the engineered immune cell/pharmaceutical composition for treating cancers.

Abstract: The present disclosure provides an event extraction method, an event extraction device and an electronic device, and it relates to the field of computer data processing, in particular to the field of knowledge graph. The event extraction method includes: acquiring text information; determining a plurality of pieces of question information ranked in a sequential order in accordance with the text information; and inputting vector information for each piece of question information into an extraction model in accordance with the sequential order to acquire extraction information for each piece of question information.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: Provided are an ROR1-targeting antibody, and a multispecific antibody, a chimeric antigen receptor, an antibody conjugate, a pharmaceutical composition and a kit which comprise same, and the use thereof in the diagnosis/treatment/prevention of diseases associated with ROR1 expression.

Abstract: An engineered immune cell, which expresses (i) a cell surface molecule that specifically recognizes a ligand, (ii) an exogenous interleukin, and (iii) an exogenous Flt3L, XCL2, and/or XCL1; the engineered immune cell can be used for treating cancer, infection, or autoimmune diseases; and compared with a traditional engineered immune cell, the engineered immune cell has significantly improved tumor killing activity.

Abstract: A module assembly is provided including a fuel cell stack assembly, a heat exchanger, and a housing enclosing the fuel cell stack assembly and the heat exchanger. The heat exchanger is configured to receive process gas from an external source and output said process gas to the fuel cell stack assembly, and configured to receive process gas from the fuel cell stack assembly and output said process gas. A fuel cell power plant is provided including a module assembly with a first end, a racking structure configured to hold the module assembly, balance of plant equipment, and ducting configured to provide fluid communication between the balance of plant equipment and the first end of the module assembly. The module assembly and the racking structure are configured such that the module assembly may be removed from the racking structure in a direction away from the first end of the module assembly.

Abstract: Provided are an NKG2A-targeting antibody, and a multispecific antibody, a chimeric receptor, an antibody conjugate, a pharmaceutical composition and a kit which comprise same, and the use thereof in the diagnosis/treatment/prevention of diseases associated with NKG2A expression.