Abstract: An output driver circuit having an input stage and an output stage, wherein the output stage and the input stage are configured to function as (1) a low-frequency voltage follower and (2) a high-frequency feedback loop for the output driver circuit. In operation, the low-frequency follower and the high-frequency feedback loop may precisely regulate the output voltage of the output driver circuit when large load transients occur. A compact charge pump may be used to supply additional voltage required to operate a current mirror of the output driver circuit.

Abstract: A data processing system (100), such as a System-on-Chip, includes a processor (120), a memory (140) that has an expected minimum data retention voltage, and a brown-out detector (160), which includes a brown-out detection circuit (201) that has an analog output, and an output circuit (248 and 252) that converts the analog output of the brown-out detection circuit to a digital brown-out flag. The brown-out detection circuit includes a self-biased current reference, current mirrors, and a current comparator. The brown-out detector monitors voltage of a power supply of the memory, and the brown-out detector asserts the digital brown-out flag to the processor when the voltage of the power supply is at, or slightly above, a highest expected minimum data retention voltage.

Abstract: A brown-out detection circuit includes a first resistive element, a first transistor, a second transistor, and a comparator. The first resistive element has a first terminal coupled to a first power supply voltage terminal, and a second terminal. The first transistor is of a first conductivity type and has a first current electrode coupled to the second terminal of the first resistive element, a control electrode, and a second current electrode. The second transistor is of a second conductivity type and has a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal. The comparator has a first input terminal coupled to the first terminal of the first resistive element, a second input terminal coupled to the second terminal of the first resistive element, and an output terminal for providing a brown-out detection signal.

Abstract: A switched-capacitor amplifier circuit (200 and 300) with rail-to-rail capability without requiring a rail-to-rail operational amplifier includes a switched-capacitor amplifier (202 and 302) and an input network (201) coupled to the switched-capacitor amplifier. The switched-capacitor amplifier includes a non-rail-to-rail operational amplifier (275 and 375). The input network prevents the non-rail-to-rail operational amplifier from receiving an input differential signal that has a common-mode voltage at or near rails of the non-rail-to-rail operational amplifier. Voltages at input terminals of the operational amplifier remain near analog ground, which is an arbitrary voltage level between the rails, during both phases of switching in the switched-capacitor amplifier. In one embodiment, the switched-capacitor amplifier uses a correlated double sampling technique.

Abstract: A data processing system (100), such as a System-on-Chip, includes a processor (120), a memory (140) that has an expected minimum data retention voltage, and a brown-out detector (160), which includes a brown-out detection circuit (201) that has an analog output, and an output circuit (248 and 252) that converts the analog output of the brown-out detection circuit to a digital brown-out flag. The brown-out detection circuit includes a self-biased current reference, current mirrors, and a current comparator. The brown-out detector monitors voltage of a power supply of the memory, and the brown-out detector asserts the digital brown-out flag to the processor when the voltage of the power supply is at, or slightly above, a highest expected minimum data retention voltage.

Abstract: A low voltage detector (100) includes a voltage and current reference circuit (102); a power supply voltage monitor circuit (104), coupled to the voltage and current reference circuit and to a power supply; and a voltage comparator (106), coupled to the voltage and current reference circuit and to the power supply voltage monitor circuit. The voltage and current reference circuit includes a self-cascode MOSFET structure (SCM) (110) that produces a reference voltage. The power supply voltage monitoring circuit includes another SCM (140) that produces a monitor voltage, related to the power supply voltage. The reference voltage and the monitor voltage have a same behavior with changes in temperature, thereby allowing the trip point of the low voltage detector to minimally vary with temperature. The low voltage detector is disposed on an integrated circuit (101), and the transistors of the low voltage detector consist of only CMOS transistors.

Abstract: A programmable voltage reference includes a temperature compensated current source and a voltage reference circuit. The temperature compensated current source includes an output configured to provide a reference current. The voltage reference circuit includes an input coupled to the output of the temperature compensated current source and a reference output. The voltage reference circuit includes a self-cascode metal-oxide semiconductor field-effect transistor structure that includes a first device that is diode-connected and operates in a weak inversion saturation region and a second device that operates in a weak inversion triode region. A length of the second device is selectable. The voltage reference circuit is configured to provide a reference voltage on the reference output based on the reference current.

Abstract: A test structure (200) in an integrated circuit (100) includes a probe pad (210) disposed at a surface of a die (102) of the integrated circuit, a transmission gate (202) for connecting portions of an electronic circuit within the integrated circuit in response to a momentary signal applied to the probe pad, a first inverter (221) having an input coupled to the probe pad and having an output coupled to a control input of the transmission gate, and a second inverter (222) having an input coupled to an output of the first inverter and having an output coupled to another control input of the transmission gate. The output of the second inverter is coupled to the input of the first inverter. Upon power-up, the transmission gate is open. After the momentary signal is applied to the probe pad, the transmission gate closes and remains closed until power is disconnected.

Abstract: A brown-out detection circuit comprises a first resistive element, a first transistor, a second transistor, and a comparator. The first resistive element has a first terminal coupled to a first power supply voltage terminal, and a second terminal. The first transistor is of a first conductivity type and has a first current electrode coupled to the second terminal of the first resistive element, a control electrode, and a second current electrode. The second transistor is of a second conductivity type and has a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal. The comparator has a first input terminal coupled to the first terminal of the first resistive element, a second input terminal coupled to the second terminal of the first resistive element, and an output terminal for providing a brown-out detection signal.

Abstract: A bandgap voltage reference unit on an integrated circuit (101) includes a proportional-to-absolute-temperature (PTAT) current source (100) coupled to a bandgap voltage reference circuit (200) that includes a plurality of self-cascode MOSFET structures (201-204) that are cascaded together to form a PTAT voltage generator (205). The bandgap voltage reference circuit also includes a complementary-to-absolute-temperature (CTAT) device (260). A PTAT voltage from the PTAT voltage generator is added to a CTAT voltage from the CTAT device to produce an output voltage of the bandgap voltage reference unit, such that the output voltage is the bandgap voltage of the integrated circuit and such that the output voltage does not change with temperature.

Abstract: A non-volatile memory cell and method for reading it are disclosed. In one embodiment, the non-volatile memory cell includes a fuse with a first terminal coupled to a first power supply voltage terminal, and a second terminal, a first transistor having a first current electrode coupled to the second terminal of the programmable fuse, a second current electrode, and a control electrode, and a second transistor having a first current electrode connected to the first power supply voltage terminal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the control electrode. By applying a read signal to the control electrode of the first transistor, the state of the cell (blown or unblown) is read.

Abstract: A programmable voltage reference includes a temperature compensated current source and a voltage reference circuit. The temperature compensated current source includes an output configured to provide a reference current. The voltage reference circuit includes an input coupled to the output of the temperature compensated current source and a reference output. The voltage reference circuit includes a self-cascode metal-oxide semiconductor field-effect transistor structure that includes a first device that is diode-connected and operates in a weak inversion saturation region and a second device that operates in a weak inversion triode region. A length of the second device is selectable. The voltage reference circuit is configured to provide a reference voltage on the reference output based on the reference current.

Abstract: Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.

Abstract: Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.

Abstract: A non-volatile memory cell 100 includes a static latch 125 having a first terminal and a second terminal, a first transistor 124 having a first current electrode coupled to said first terminal of said static latch 125 and a fusible element 110 having a first terminal coupled to a second current electrode of the first transistor 125 and a second terminal coupled to a first power supply voltage terminal. In a particular embodiment, the non-volatile memory cell includes a fusible element programming circuit 140 coupled to the first terminal of said fusible element. In another particular embodiment, the non-volatile memory cell includes a cell preset circuit 120 coupled to a control electrode of the first transistor.

Abstract: An electric toothbrush comprising a cylindrical casing; at least one disposable cylinder within the casing to hold; a hollow neck affixed to the casing for permitting the flow of gel there through; and a hollow tooth implement rotatably affixed to the throat, said tooth implement comprising a brush, flosser or scraper.

Abstract: Application of nanoparticles based on hydrophilic polymers as pharmaceutical forms for the administration of active macromolecules. The nanoparticles (having a nanometric size and a hydrophilic character), also called nanospheres or latex, are colloidal systems comprised of the combination of hydrophilic polymers and an active ingredient having a high molecular weight (active macromolecule, molecular weight higher than 1000 daltons). The hydrophilic polymers are the chitosan (an aminopolysaccharide) or its derivatives and polyoxyethylene or its derivatives. The association of the active macromolecule to said nanoparticles takes place in an aqueous phase without having to use organic solvents or auxiliary toxic substances. The active ingredient charge capacity of the nanoparticles is extremely high and additionally said charge is released in a controlled and time extended way. Additionally, said nanoparticles have a positive surface electric charge whose intensity may vary in relation to its composition.

Abstract: The method of treating a leukotriene-mediated disease which is treatable by inhibition of 5-lipoxygenase includes administering a therapeutically effective amount of 2,4,6-triiodophenol, or a pharmaceutically acceptable salt or solvate thereof, for 5-lipoxygenase inhibition, together with an adequate amount of pharmaceutically acceptable excipients, diluents or carriers to the patient suffering from the disease. The diseases treated advantageously include, among others, herpes and gastrointestinal, respiratory, skin and/or ocular inflammatory diseases.

Abstract: Stabilization of colloidal systems through the formation of lipid-polyssacharide complexes. Development of a procedure for the preparation of colloidal systems involving a combination of two ingredients: a water soluble and positively charged polyssacharide and a negatively charged phospholipid. Colloidal systems (submicron emulsions and polymeric nanoparticles and nanocapsules) are stabilized through the formation, at the interface, of an ionic complex: aminopolyssachride-phospholipid. These colloidal systems are characterized by their positive charge and their improved stability. Furthermore, they can be freeze-dried, stored in a dry state and hydrated when required. They can be interesting systems for the administration of drugs by the oral, transdermal, ocular, nasal and vaginal routes of administration. In addition, they can be of interest for cosmetic use.