Abstract: A heat sink comprises a base and a fin support larger in area than the base and supporting fins that may be positioned in a plurality of orientations relative to the base. The base is adapted for being connected to a heat-generating electronic component on a circuit board, and the heat sink dissipates heat generated by the heat-generating electronic device and conducted through the base and the fin support to the fins supported thereon. The heat sink dissipates heat from the heat-generating electronic device in a first operable position and in a second operable position. The heat sink may be moved from the first to the second operable position to facilitate access to electrical contacts proximal the heat-generating electronic component.

Abstract: Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.

Abstract: A method includes performing operations on a compute node including a plurality of processors each having a local PCI processing element and a local processor interconnect, wherein the local processor interconnect of each processor is connected to the local processor interconnect of at least one other processor. The method further includes identifying a PCI device that is directly attached to the local PCI processing element of a first one of the processors and positioned in an upstream airflow direction from the first processor. The operating system monitors the PCI device and, in response to determining that the PCI device is performing a power-intensive operation, directs operations away from the first processor to a second one of the processors, wherein the local processor interconnect of the second processor is directly connected to the processor interconnect of the first processor.

Abstract: The present disclosure provides signaling control among multiple communication interfaces of an electronic device based on signal priority. According to an aspect, an electronic device includes multiple communication interfaces. The electronic device also includes a communication controller configured to determine priority of signals to be communicated on different communication interfaces among the plurality of communication interfaces. Further, the communication controller is configured to determine an order of communication of the signals among the different communication interfaces based on the priority of the signals to be communicated. The communication controller is also configured to control communication of the signals among the different communication interfaces based on the determined order of communication.

Abstract: An electronic system comprises: a pin sensor; and an integrated management module, wherein the integrated management module: identifies a location of a damaged connector between a semiconductor chip and a hardware socket, wherein the location of the damaged connector is described by one or more readings from the pin sensor, and wherein the damaged connector prevents a particular signal from being supplied to the semiconductor chip via the hardware socket; identifies the particular signal as an input for a particular semiconductor function; determines whether the semiconductor chip provides the particular semiconductor function; and adjusts a use of the semiconductor chip based on whether or not the semiconductor chip uses the particular signal to provide the particular semiconductor function.

Abstract: A power device powers a hardware component and a fan cools the component. A primary management device monitors a first characteristic, which is the temperature of the component or the power provided by the power device, and determines a desired fan speed of the fan based on the first characteristic. A secondary management device monitors a second characteristic, which is the temperature of the component or the power provided by the power device, and sets the fan speed to the desired fan speed determined by the primary management device. The secondary management device constructs a profile of the fan speed in relation to the second characteristic by periodically recording the fan speed and the second characteristic. In response to the primary management device failing, the secondary management device determines the desired fan speed based on the profile and set the fan speed to the desired fan speed that it determined.

Abstract: A computer program product includes a computer readable storage medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to perform a method. The method comprises obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit. The method further includes dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.

Abstract: Allocating lanes in a Peripheral Connect Interface Express (‘PCIe’) bus, including: determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device.

Abstract: A computer memory system comprises non-volatile memory and a memory controller module including a memory controller. The memory controller module is selectively secured in a memory module socket of a motherboard to provide the memory controller in communication with a memory module bus using a memory bus standard. The memory controller includes one or more ports for communication with the non-volatile memory using a data storage protocol, wherein the memory controller controls read and write operations for the non-volatile memory. The memory system further comprises one or more cables connecting the one or more ports of the memory controller to the non-volatile memory, wherein the non-volatile memory is not on the memory controller module. Optionally, the non-volatile memory may be included in a separate memory module or a solid state drive.

Abstract: A method and computer program product for performing the method are provided. The method includes managing network traffic, such as data files and data streams, for a network device, and identifying a context, such as a source address, subject matter, file type, file size, and data streaming rate, associated with each of the network objects. The method further includes obtaining user data associated with the network device, for example a plurality of activities, such as schedule events and historical behavior, and a time associated with each activity. Still further, the method comprises correlating network objects to activities, and altering prioritization of the network objects that are correlated with the activities in response to a current time being within a predetermined time period of the time associated with the one or more activities.

Abstract: A method includes identifying a plurality of power supplies connected for supplying power to a computer system, wherein the plurality of power supplies includes at least one redundant power supply in a standby mode. For each of the plurality of power supplies identified, the method determines a length of a power supply cable connected between the power supply and a power distribution unit for supplying power to the power supply. The method further includes placing one or more of the plurality of power supplies in an active mode in ascending order of the length of the cable connected to the power supply, and supplying power to the computer system using the one or more of the plurality of power supplies in the active mode.

Abstract: An apparatus includes a display screen including a first array of first light-emitting diodes for emitting visible light and a second array of second light-emitting diodes for emitting ultraviolet light, wherein the second light-emitting diodes are interspersed among the first light-emitting diodes. A method includes a computing device receiving input from a remote server indicating that a surface of the computing device should be disinfected, the computing device detecting that a display screen is in a closed positioning facing the surface, wherein the display screen includes an array of light-emitting diodes for emitting ultraviolet light, and controlling operation of the light-emitting diodes to disinfect the surface in response to the input received. The surface may, for example, be selected from a keyboard, a touchpad, and a cover.

Abstract: Embodiments of the invention provide a method, system and computer program product for dynamically locating a device within a data center. A method for dynamically locating a device within a data center includes wirelessly receiving in a fixed device amongst a multiplicity of devices in a data center, a request from a mobile device to locate a target device amongst the devices. The method also includes broadcasting a request to the multiplicity of devices to establish respective wireless identifiers based upon a proximity of each of the multiplicity of the devices to the target device relative to adjacent ones of the devices. The method yet further includes establishing a wireless identifier for the fixed device based upon a wireless identifier of an adjacent one of the devices. Finally, the method includes returning to the mobile device by the fixed device the established wireless identifier for the fixed device.

Abstract: A method includes performing operations on a compute node including a plurality of processors each having a local PCI processing element and a local processor interconnect, wherein the local processor interconnect of each processor is connected to the local processor interconnect of at least one other processor. The method further includes identifying a PCI device that is directly attached to the local PCI processing element of a first one of the processors and positioned in an upstream airflow direction from the first processor. The operating system monitors the PCI device and, in response to determining that the PCI device is performing a power-intensive operation, directs operations away from the first processor to a second one of the processors, wherein the local processor interconnect of the second processor is directly connected to the processor interconnect of the first processor.

Abstract: A hardware system comprises a digital signal generator, which generates a digital electrical signal that describes a first physical state of a first device; an analog electrical signal generator, which generates an analog electrical signal that describes a second physical state of the first device; a hybrid digital state signal generator, which generates a hybrid digital state signal that comprises the analog electrical signal overlaid onto the initial digital electric signal; and a hybrid signal transmitter, which transmits the hybrid digital state signal from the first device to a second device, wherein the second device comprises a hybrid signal receiver/decoder that extracts the analog electrical signal from the hybrid digital state signal.

Abstract: Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

Abstract: A method, system, and/or computer program product allocates network addresses to network devices. A network address providing server designates a particular network address as a designated network address for use with a specific non-network device, where the specific non-network device has a Unique Device Capability Identifier (UDCI), and where the non-network device is not connected to a network. The designated network address is stored in a lookup table containing the UDCI, such that the lookup table associates the designated network address with the UDCI. In response to a request from a network device for a network address including the UDCI, the network address providing server retrieves the designated network address from the lookup table based on the UDCI found in the request for a network address. The designated network address is then sent to the network device for use as a network address of the network device.

Abstract: Detecting TIM between a heat sink and an integrated circuit, the heat sink including TIM detection points, each TIM detection point adapted to receive TIM upon installation of the heat sink, each TIM detection point including a TIM detection device configured to be activated upon contact with TIM, including: receiving, upon installation of the heat sink on the integrated circuit and the TIM, TIM in one or more of the TIM detection points; activating, by the TIM in each of the one or more TIM detection points receiving the TIM, a TIM detection device; and determining, by a TIM detection module in dependence upon the activations of the TIM detection devices, sufficiency of the TIM between the heat sink and the integrated circuit.

Abstract: According to one exemplary embodiment, a method for reducing electrical component stress from power cycling is provided. The method may include receiving an indication associated with power cycling an electronic apparatus. The method may also include identifying, based on the received indication, a first one or more groups of electrical components that will not be powered off during the power cycling of the electronic apparatus. The method may further include identifying, based on the received indication, a second one or more groups of electrical components that will be powered off during the power cycling of the electronic apparatus. The method may finally include powering off the second one or more groups of electrical components.

Abstract: A method includes sensing ambient conditions in a datacenter containing a server, and determining whether the ambient conditions exceed threshold conditions representing risk of electrostatic discharge. A lid to the server is locked in a closed position in response to the ambient conditions exceeding the threshold conditions. However, the lid to the server is unlocked in response to a grounding strap being connected to the server. Optionally, the grounding strap may be identified and the server lid will only unlock if the identified grounding strap is associated with authorization to unlock the server lid.