Abstract: According to one exemplary embodiment, a method for load optimization using cable-associated voltage drop is provided. The method may include receiving a plurality of tasks for processing by a plurality of electronic devices. The method may also include determining a power loss value for one or more power cables powering each of the plurality of electronic devices. The method may further include assigning the plurality of tasks to one or more of the plurality of electronic devices based on the power loss value for the one or more power cables powering each of the plurality of electronic devices.

Abstract: Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.

Abstract: A method includes regulating voltage to a memory system responsive to a voltage signal received at a voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations within the memory system. The method further includes identifying a location of each of a plurality of installed memory modules present in the memory system. Still further, the method includes identifying a voltage sense line pair that provides a shortest aggregate distance to each of the installed memory modules, and then regulating voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: A computer program product includes a computer readable storage medium embodying program instructions executable by a processor to perform a method. The method includes sequentially passing a voltage signal from each voltage sense line pair to a voltage feedback line of a voltage regulator. The voltage regulator controls voltage to the memory system responsive to the voltage signal received at the voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations. For each voltage sense line pair, the method identifies a memory margin based on memory operation while regulating voltage responsive to the voltage signal from the voltage sense line pair. The voltage sense line pair that provides the greatest memory margin is identified, and the voltage regulator is made to control voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: Dividing a single phase PWM signal into a plurality of phases includes: receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period; and dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train: providing, on a next output phase of the PWM frequency divider, an output pulse train; and holding all other output phases at a tri-state voltage level.

Abstract: Embodiments of the invention provide a method, system and computer program product for dynamically locating a device within a data center. A method for dynamically locating a device within a data center includes wirelessly receiving in a fixed device amongst a multiplicity of devices in a data center, a request from a mobile device to locate a target device amongst the devices. The method also includes broadcasting a request to the multiplicity of devices to establish respective wireless identifiers based upon a proximity of each of the multiplicity of the devices to the target device relative to adjacent ones of the devices. The method yet further includes establishing a wireless identifier for the fixed device based upon a wireless identifier of an adjacent one of the devices. Finally, the method includes returning to the mobile device by the fixed device the established wireless identifier for the fixed device.

Abstract: Systems and methods for allocating memory usage based on voltage regulator efficiency are disclosed. According to an aspect, a method may include receiving a first efficiency value of a first voltage regulator associated with a first memory device among multiple memory devices. The method may also include receiving a second efficiency value of a second voltage regulator associated with a second memory device of the memory devices. The method may also include receiving a request to write data to one of the first memory devices and the second memory device. The method may also include determining whether to write the data to the first memory device or the second memory device based on the first and second efficiency values. Further, the method may include writing the data to the first memory device or the second memory device based on the determination.

Abstract: Reconfigurable processors and methods for collecting computer program instruction execution statistics are disclosed. According to an aspect, a method includes providing a reconfigurable processor configured to execute a set of central processing unit (CPU) instructions that each have a function. The method also includes modifying the function of one or more of the CPU instructions that identifies an instruction address and a destination address pair of the CPU instruction(s) based on a defined test case. Further, the method includes using the reconfigurable processor to execute the set of CPU instructions. The method also includes identifying an instruction address and destination address pair of the CPU instruction(s) having the modified function when the CPU instruction(s) having the modified function is executed during execution of the set of CPU instructions.

Abstract: A method includes sensing ambient conditions in a datacenter containing a server, and determining whether the ambient conditions exceed predetermined threshold conditions representing risk of electrostatic discharge. A lid to the server is locked in a closed position in response to the ambient conditions exceeding the predetermined threshold conditions. However, the lid to the server is unlocked in response to a grounding strap being connected to the server. Optionally, the grounding strap may be identified and the server lid will only unlock if the identified grounding strap is associated with authorization to unlock the server lid.

Abstract: The present disclosure provides signaling control among multiple communication interfaces of an electronic device based on signal priority. According to an aspect, an electronic device includes multiple communication interfaces. The electronic device also includes a communication controller configured to determine priority of signals to be communicated on different communication interfaces among the plurality of communication interfaces. Further, the communication controller is configured to determine an order of communication of the signals among the different communication interfaces based on the priority of the signals to be communicated. The communication controller is also configured to control communication of the signals among the different communication interfaces based on the determined order of communication.

Abstract: An electronic system comprises: a pin sensor; and an integrated management module, wherein the integrated management module: identifies a location of a damaged connector between a semiconductor chip and a hardware socket, wherein the location of the damaged connector is described by one or more readings from the pin sensor, and wherein the damaged connector prevents a particular signal from being supplied to the semiconductor chip via the hardware socket; identifies the particular signal as an input for a particular semiconductor function; determines whether the semiconductor chip provides the particular semiconductor function; and adjusts a use of the semiconductor chip based on whether or not the semiconductor chip uses the particular signal to provide the particular semiconductor function.

Abstract: A system, method, and/or computer program product comprises an input/output (I/O) bus and an intelligent current bank that couples a voltage source to the I/O bus. The intelligent current bank includes an ammeter that measures a real-time flow of current to the I/O bus. In response to the current to the I/O bus exceeding a predetermined level, an intelligent Pulse-Width Modulator (iPWM) within the intelligent current bank selectively decreases current to one or more electronic devices on the I/O bus by shortening a duty cycle of voltage being received by the iPWM from the voltage source.

Abstract: Dividing a single phase PWM signal into a plurality of phases includes: receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period; and dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train: providing, on a next output phase of the PWM frequency divider, an output pulse train; and holding all other output phases at a tri-state voltage level.

Abstract: Detecting TIM between a heat sink and an integrated circuit, the integrated circuit including TIM detection points adapted to receive TIM upon installation of the heat sink and including a TIM detection device configured to be activated upon contact with TIM, including: receiving, upon installation of the heat sink on the integrated circuit and the TIM, TIM in one or more of the TIM detection points; activating, by the TIM in each of the one or more TIM detection points receiving the TIM, a TIM detection device; determining, by a TIM detection module of the integrated circuit in dependence upon the activations of the TIM detection devices, sufficiency of the TIM; and responsive to determining that the TIM between the heat sink and the integrated circuit is insufficient, controlling, in real-time by the TIM detection module, operation of the integrated circuit to reduce heat generated by the integrated circuit.

Abstract: A computer program product (CPP) for controlling a liquid crystal display (LCD) includes code for applying a test voltage to each liquid crystal element (LCE) disposed in an addressable array forming the LCD, and code for detecting an amount of light received by photosensors while applying the test voltage to the LCEs, wherein each photosensor is aligned behind and logically associated with one of the LCEs. The CPP further includes code for applying selected voltage levels to each LCE to display an image, and code for controlling an amount of backlight produced by backlighting elements in an addressable array while the image is displayed. Each backlighting element is aligned behind and logically associated with one LCE, and at least one backlighting element is controlled to compensate for a difference between the amount of light detected by the photosensor logically associated with at least one LCE and the other photosensors.

Abstract: Thermally sensitive wear leveling for a flash memory device that includes a plurality of flash memory modules, the flash memory device included in a computing system that includes a plurality of additional computing components, including: identifying a thermal sensitivity coefficient for each flash memory module in dependence upon a physical topology of the flash memory device and one or more of the additional computing components; identifying wear leveling information for each flash memory module; receiving a request to write data to the flash memory device; selecting, in dependence upon the thermal sensitivity coefficient for each flash memory module and the wear leveling information for each flash memory module, a target flash memory module for servicing the request to write data to the flash memory device; and writing the data to the target flash memory module.

Abstract: A computer program product includes a computer readable storage medium embodying program instructions executable by a processor to perform a method. The method includes sequentially passing a voltage signal from each voltage sense line pair to a voltage feedback line of a voltage regulator. The voltage regulator controls voltage to the memory system responsive to the voltage signal received at the voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations. For each voltage sense line pair, the method identifies a memory margin based on memory operation while regulating voltage responsive to the voltage signal from the voltage sense line pair. The voltage sense line pair that provides the greatest memory margin is identified, and the voltage regulator is made to control voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: A method includes regulating voltage to a memory system responsive to a voltage signal received at a voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations within the memory system. The method further includes sequentially passing a voltage signal from each of the voltage sense line pairs to the voltage feedback line, and, for each voltage sense line pair, calculating a memory margin of the memory system based on memory operation while regulating voltage to the memory system responsive to the voltage signal from the voltage sense line pair. Still further, the method includes identifying the voltage sense line pair that provides the greatest memory margin, and then regulating voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: Thermally sensitive wear leveling for a flash memory device that includes a plurality of flash memory modules, the flash memory device included in a computing system that includes a plurality of additional computing components, including: identifying a thermal sensitivity coefficient for each flash memory module in dependence upon a physical topology of the flash memory device and one or more of the additional computing components; identifying wear leveling information for each flash memory module; receiving a request to write data to the flash memory device; selecting, in dependence upon the thermal sensitivity coefficient for each flash memory module and the wear leveling information for each flash memory module, a target flash memory module for servicing the request to write data to the flash memory device; and writing the data to the target flash memory module.

Abstract: Controlling power consumption of a voltage regulator in a computer system that includes computer memory and the voltage regulator is configured to provide regulated source voltage to the computer memory includes: receiving, by a voltage regulator controller, memory margin statistics of the computer memory, the memory margin statistics including data describing operational tolerance of the computer memory to source voltage signal variations; and adjusting, by the voltage regulator controller, one or more operating characteristics of the voltage regulator in dependence upon the memory margin statistics.