Patents by Inventor Madhava Rao Yalamanchili

Madhava Rao Yalamanchili has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140377937
    Abstract: Methods of using a hybrid mask composed of a first water soluble film layer and a second water-soluble layer for wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a hybrid mask above the semiconductor wafer. The hybrid mask is composed of a first water-soluble layer disposed on the integrated circuits, and a second water-soluble layer disposed on the first water-soluble layer. The method also involves patterning the hybrid mask with a laser scribing process to provide a patterned hybrid mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also involves etching the semiconductor wafer through the gaps in the patterned hybrid mask to singulate the integrated circuits.
    Type: Application
    Filed: September 5, 2014
    Publication date: December 25, 2014
    Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Todd Egan, Madhava Rao Yalamanchili, Ajay Kumar
  • Publication number: 20140367041
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
    Type: Application
    Filed: September 3, 2014
    Publication date: December 18, 2014
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
  • Patent number: 8912077
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: December 16, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Saravjeet Singh, Brad Eaton, Ajay Kumar, Wei-Sheng Lei, James M. Holden, Madhava Rao Yalamanchili, Todd J. Egan
  • Publication number: 20140363952
    Abstract: Front side laser scribing and plasma etch are performed followed by back side grind to singulate integrated circuit chips (ICs). A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to advance a front of an etched trench partially through the semiconductor wafer thickness. The front side mask is removed, a backside grind tape applied to the front side, and a back side grind performed to reach the etched trench, thereby singulating the ICs.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar
  • Publication number: 20140346641
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, approaches for wafer dicing with wide kerf by using a laser scribing and plasma etching hybrid approach are described. For example, a method of dicing a semiconductor wafer including a plurality of integrated circuits separated by dicing streets involves forming a mask above the semiconductor wafer, the mask having a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide a patterned mask having a pair of parallel gaps for each dicing street, exposing regions of the semiconductor wafer between the integrated circuits. Each gap of each pair of parallel gaps is separated by a distance. The method also involves etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: July 22, 2013
    Publication date: November 27, 2014
    Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Madhava Rao Yalamanchili, Ajay Kumar
  • Publication number: 20140335679
    Abstract: In some embodiments, a method for etching features into a substrate may include exposing a substrate having a photoresist layer disposed atop the substrate to a first process gas to form a polymer containing layer atop sidewalls and a bottom of a feature formed in the photoresist layer, wherein the first process gas is selectively provided to a first area of the substrate via a first set of gas nozzles disposed within a process chamber and; exposing the substrate to a second process gas having substantially no oxygen to etch the feature into the substrate, wherein the second process gas is selectively provided to a second area of the substrate via a second set of gas nozzles disposed in the process chamber.
    Type: Application
    Filed: July 9, 2013
    Publication date: November 13, 2014
    Inventors: TONG LIU, DAVID REYLAND, ROHIT MISHRA, KHALID MOHIUDDIN SIRAJUDDIN, MADHAVA RAO YALAMANCHILI, AJAY KUMAR
  • Patent number: 8883614
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, approaches for wafer dicing with wide kerf by using a laser scribing and plasma etching hybrid approach are described. For example, a method of dicing a semiconductor wafer including a plurality of integrated circuits separated by dicing streets involves forming a mask above the semiconductor wafer, the mask having a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide a patterned mask having a pair of parallel gaps for each dicing street, exposing regions of the semiconductor wafer between the integrated circuits. Each gap of each pair of parallel gaps is separated by a distance. The method also involves etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: November 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Apama Iyer, Madhava Rao Yalamanchili, Ajay Kumar
  • Patent number: 8859397
    Abstract: Methods of using a hybrid mask composed of a first water soluble film layer and a second water-soluble layer for wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a hybrid mask above the semiconductor wafer. The hybrid mask is composed of a first water-soluble layer disposed on the integrated circuits, and a second water-soluble layer disposed on the first water-soluble layer. The method also involves patterning the hybrid mask with a laser scribing process to provide a patterned hybrid mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also involves etching the semiconductor wafer through the gaps in the patterned hybrid mask to singulate the integrated circuits.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: October 14, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Todd Egan, Madhava Rao Yalamanchili, Ajay Kumar
  • Patent number: 8853056
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: October 7, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
  • Patent number: 8845854
    Abstract: Front side laser scribing and plasma etch are performed followed by back side grind to singulate integrated circuit chips (ICs). A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to advance a front of an etched trench partially through the semiconductor wafer thickness. The front side mask is removed, a backside grind tape applied to the front side, and a back side grind performed to reach the etched trench, thereby singulating the ICs.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: September 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar
  • Patent number: 8846498
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a multi-step laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: September 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar
  • Publication number: 20140273401
    Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a mask comprising a laser energy absorbing material layer soluble in water over the semiconductor substrate. The laser energy absorbing material layer may be UV curable, and either remain uncured or be cured prior to removal with a water rinse. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the laser energy absorbing mask protecting the ICs for during the plasma etch. The soluble mask is then dissolved subsequent to singulation.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Inventors: Wei-Sheng LEI, Brad EATON, Aparna IYER, Saravjeet SINGH, Madhava Rao YALAMANCHILI, Ajay KUMAR
  • Publication number: 20140273460
    Abstract: Embodiments of the present disclosure generally provide apparatus and methods for improving process result near the edge region of a substrate being processed. One embodiment of the present disclosure provides a cover ring for improving process uniformity. The cover ring includes a ring shaped body, and an extended lip extending radially inwards from the ring shaped body. An inner edge of the extended lip forms a central opening to expose a processing region on a substrate being processed, and a width of the extended lip is between about 15% to about 20% of a radius of the central opening.
    Type: Application
    Filed: February 20, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: David REYLAND, Dung Huu LE, Saravjeet SINGH, Madhava Rao YALAMANCHILI
  • Publication number: 20140213042
    Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a mask, patterning the mask with a femtosecond laser scribing process to provide a patterned mask with gaps, and ablating through an entire thickness of a semiconductor substrate to singulate the IC. Following laser-based singulation, a plasma etch is performed to remove a layer of semiconductor sidewall damaged by the laser scribe process. In the exemplary embodiment, a femtosecond laser is utilized and a 1-3 ?m thick damage layer is removed with the plasma etch. Following the plasma etch, the mask is removed, rendering the singulated die suitable for assembly/packaging.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 31, 2014
    Inventors: Wei-Sheng LEI, Aparna IYER, Brad EATON, Madhava Rao YALAMANCHILI, Ajay KUMAR
  • Publication number: 20140199833
    Abstract: The present disclosure provides methods for via reveal etching process to form through-silicon vias (TSVs) in a substrate. In one embodiment, a method for performing a via reveal process to form through-silicon vias in a substrate includes providing a substrate having partial through-silicon vias formed from a first surface of the substrate into a processing chamber, wherein the partial through-silicon vias formed in the substrate are blind vias, supplying an etching gas mixture including at least a fluorine containing gas and a chlorine containing gas into the processing chamber, and preferentially removing a portion of the substrate from a second surface of the substrate to expose the through-silicon vias until a desired length of the through-silicon vias is exposed from the second surface of the substrate.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 17, 2014
    Applicant: Applied Materials, Inc.
    Inventors: Rohit MISHRA, Khalid Mohiuddin SIRAJUDDIN, Madhava Rao YALAMANCHILI, Sonal A. SRIVASTAVA
  • Publication number: 20140179108
    Abstract: Embodiments of the invention generally relate to an apparatus and method for plasma etching. In one embodiment, the apparatus includes a process ring with an annular step away from an inner wall of the ring and is disposed on a substrate support in a plasma process chamber. A gap is formed between the process ring and a substrate placed on the substrate support. The annular step has an inside surface having a height ranging from about 3 mm to about 6 mm. During operation, an edge-exclusion gas is introduced to flow through the gap and along the inside surface, so the plasma is blocked from entering the space near the edge of the substrate.
    Type: Application
    Filed: March 4, 2013
    Publication date: June 26, 2014
    Inventors: Dung Huu Le, Graeme Jamieson Scott, Jivko Dinev, Madhava Rao Yalamanchili, Khalid Mohiuddin Sirajuddin, Puneet Bajaj, Saravjeet Singh
  • Publication number: 20140179084
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. For example, a method includes applying a protection tape to a wafer front side, the wafer having a dicing tape attached to the wafer backside. The dicing tape is removed from the wafer backside to expose a die attach film disposed between the wafer backside and the dicing tape. Alternatively, if no die attach film is initially disposed between the wafer backside and the dicing tape, a die attach film is applied to the wafer backside at this operation. A water soluble mask is applied to the wafer backside. Laser scribing is performed on the wafer backside to cut through the mask, the die attach film and the wafer, including all layers included within the front side and backside of the wafer. A plasma etch is performed to treat or clean surfaces of the wafer exposed by the laser scribing. A wafer backside cleaning is performed and a second dicing tape is applied to the wafer backside.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 26, 2014
    Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Saravjeet Singh, Madhava Rao Yalamanchili, Ajay Kumar
  • Publication number: 20140174659
    Abstract: Methods of dicing substrates having a plurality of ICs are disclosed. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer is washed off.
    Type: Application
    Filed: February 25, 2014
    Publication date: June 26, 2014
    Inventors: Wei-Sheng Lei, Saravjeet Singh, Madhava Rao Yalamanchili, Brad Eaton, Ajay Kumar
  • Publication number: 20140144585
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 29, 2014
    Inventors: Saravjeet Singh, Brad Eaton, Ajay Kumar, Wei-Sheng Lei, James M. Holden, Madhava Rao Yalamanchili, Todd J. Egan
  • Publication number: 20140120698
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a multi-step laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar