Abstract: Embodiments described herein generally relate to a substrate processing system and related methods, such as an etching/deposition method. The method comprises (A) depositing a protective layer on a first layer disposed on a substrate in an etch reactor, wherein a plasma source power of 4,500 Watts or greater is applied while depositing the protective layer, (B) etching the protective layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the protective layer, and (C) etching the first layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the first layer, wherein a time for the depositing a protective layer (A) comprises less than 30% of a total cycle time for the depositing a protective layer (A), the etching the protective layer (B), and the etching the first layer (C).

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a pulse train laser scribing process using multiple-pulse bursts to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer washed off.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The patterned mask is then separated from the singulated integrated circuits.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a galvanic laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: Methods of dicing substrates by both laser scribing and plasma etching. A method includes laser ablating material layers, the ablating leading with a first irradiance and following with a second irradiance, lower than the first. Multiple passes of a beam adjusted to have different fluence level or multiple laser beams having various fluence levels may be utilized to ablate mask and IC layers to expose a substrate with the first fluence level and then clean off redeposited materials from the trench bottom with the second fluence level. A laser scribe apparatus employing a beam splitter may provide first and second beams of different fluence from a single laser.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.

Abstract: Methods of dicing substrates by both laser scribing and plasma etching. A method includes forming an in-situ mask with a plasma etch chamber by accumulating a thickness of plasma deposited polymer to protect IC bump surfaces from a subsequent plasma etch. Second mask materials, such as a water soluble mask material may be utilized along with the plasma deposited polymer. At least some portion of the mask is patterned with a femtosecond laser scribing process to provide a patterned mask with trenches. The patterning exposing regions of the substrate between the ICs in which the substrate is plasma etched to singulate the IC and the water soluble material layer washed off.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a femtosecond-based laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A method and apparatus for cleaning a workpiece are disclosed. A gas and cleaning solution are supplied to an atomizing nozzle which atomizes the cleaning solution and sprays the top surface of a workpiece with an atomized spray. A liquid having a controlled gas content is flowed to the top surface of the workpiece from a rinse nozzle. Megasonic energy is applied from the backside of the workpiece.

Abstract: A method and system for cleaning a substrate is provided. More particularly systems and methods that allows for precise tailoring of megasonics distribution at a substrate surface to be above the threshold required for particle removal efficiency (PRE), yet below the value which causes structural damage are provided. This method utilizes multiple megasonics transducers operated at very low power densities in a single substrate immersion processor. This method is shown to produce high cleaning efficiencies without damage to 45 nm devices. Further, sonoluminescence studies demonstrate that the transducers are operated in the single bubble sonoluminescence (SBSL) regime, well below the cavitation threshold for transient multiple-bubble sonoluminescence (MBSL).

Abstract: A method and system for cleaning a batch of substrates is provided. The system includes a first cluster of vertical processing chambers, an IPA reservoir, and an IPA delivery system in fluid communication with the IPA reservoir and the first cluster of vertical processing chambers, wherein the IPA delivery system is adapted to transfer IPA vapor between the IPA reservoir and the first cluster of vertical processing chambers. In certain embodiments, the system further comprises a first main circulation tank, a second main circulation tank, a reservoir-cluster recirculation circuit in fluid communication with the first main circulation tank and the second main circulation tank and with each processing chamber in the first cluster of vertical processing chambers, and a dosing circuit comprising a plurality of additive sources in fluid communication with the first main circulation tank and the second main circulation tank.