Abstract: A deposition process including a dry etch process, followed by a deposition process of a high-k dielectric is disclosed. The dry etch process involves placing a substrate to be cleaned into a processing chamber to remove surface oxides. A gas mixture is energized to form a plasma of reactive gas which reacts with an oxide on the substrate, forming a thin film. The substrate is heated to vaporize the thin film and expose a substrate surface. The substrate surface is substantially free of oxides. Deposition is then used to form a layer on the substrate surface.

Abstract: Methods for preparing a substrate for a subsequent film formation process are described. Methods for preparing a substrate for a subsequent film formation process, without immersion in an aqueous solution, are also described. A process is described that includes disposing a substrate into a process chamber, the substrate having a thermal oxide surface with substantially no reactive surface terminations. The thermal oxide surface is exposed to a partial pressure of water above the saturated vapor pressure at a temperature of the substrate to convert the dense thermal oxide with substantially no reactive surface terminations to a surface with hydroxyl surface terminations. This can occur in the presence of a Lewis base such as ammonia.

Abstract: CVD and ALD methods of using a batch processing chamber to process substrates are described. A batch processing chamber includes a chamber housing, a substrate boat for containing a batch of substrates in a process region, and an excitation assembly for exciting species of a processing gas. The excitation assembly is positioned within the chamber housing and may include plasma, UV, or ion assistance.

Abstract: Atomic layer deposition methods of forming one or more of a mixed silicon oxide/silicon nitride film or a mixed silicon oxide/silicon film are described in which the substrate is exposed sequentially to a first reactant gas comprising a silicon species and a second reactant gas comprising an oxygen species to form at least a partial layer of silicon oxide on the substrate during a first atomic layer deposition process. The substrate is then exposed sequentially to a third reactant gas comprising a silicon species and a fourth reactant gas comprising a species sufficient to form at least a partial layer of one or more of silicon nitride or silicon on the substrate during a second atomic layer deposition process. The process can be repeated multiple times to deposit one or more of a mixed silicon oxide/silicon nitride film and a mixed silicon oxide/silicon film.

Abstract: Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.

Abstract: Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD.

Abstract: Embodiments of the invention provide methods for forming dielectric materials on a substrate. In one embodiment, a method includes exposing a substrate surface to a first oxidizing gas during a pretreatment process, wherein the first oxidizing gas contains a mixture of ozone and oxygen having an ozone concentration within a range from about 1 atomic percent to about 50 atomic percent and forming a hafnium-containing material on the substrate surface by exposing the substrate surface sequentially to a deposition gas and a second oxidizing gas during an atomic layer deposition (ALD) process, wherein the deposition gas contains a hafnium precursor, the second oxidizing gas contains water, and the hafnium-containing material has a thickness within a range from about 5 ? to about 300 ?. In one example, the hafnium-containing material contains hafnium oxide having the chemical formula of HfOx, whereas x is less than 2, such as about 1.8.

Abstract: Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate.

Abstract: Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.

Abstract: Embodiments of the invention provide methods for forming a hafnium material on a substrate within a processing chamber. In one embodiment, a method is provided which includes exposing the substrate within the processing chamber to a first oxidizing gas during a pretreatment process, exposing the substrate sequentially to a second oxidizing gas and a deposition gas during an atomic layer deposition (ALD) cycle, wherein the second oxidizing gas contains water and the deposition gas contains a hafnium amino compound, and repeating the ALD cycle to form a hafnium-containing layer having a thickness within a range from about 5 ? to about 300 ?. In one example, the first oxidizing gas contains an O3/O2 mixture having an ozone concentration within a range from about 5 atomic percent to about 30 atomic percent.

Abstract: The present invention generally provides method and apparatus for non-contact temperature measurement in a semiconductor processing chamber. Particularly, the present invention provides methods and apparatus for non-contact temperature measurement for temperature below 500° C. One embodiment of the present invention provides an apparatus for processing semiconductor substrates. The apparatus comprises a target component comprises a material with higher emissivity than the one or more substrates.

Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

Abstract: The present invention generally comprises a silicon dioxide atomic layer deposition method. By providing pyridine as a catalyst, water may be utilized as the oxidization source while depositing at a low temperature. Prior to exposing the substrate to the water, the substrate may be exposed to a pyridine soak process. Additionally, the water may be co-flowed to the chamber with the pyridine through separate conduits to reduce interaction prior to entering the chamber. Alternatively, the pyridine may be co-flowed with a silicon precursor that does not react with pyridine.

Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

Abstract: A batch processing chamber includes a chamber housing, a substrate boat for containing a batch of substrates in a process region, and an excitation assembly for exciting species of a processing gas. The excitation assembly is positioned within the chamber housing and may include plasma, UV, or ion assistance.

Abstract: The present invention generally comprises a silicon dioxide atomic layer deposition method. By providing pyridine as a catalyst, water may be utilized as the oxidization source while depositing at a low temperature. Prior to exposing the substrate to the water, the substrate may be exposed to a pyridine soak process. Additionally, the water may be co-flowed to the chamber with the pyridine through separate conduits to reduce interaction prior to entering the chamber. Alternatively, the pyridine may be co-flowed with a silicon precursor that does not react with pyridine.

Abstract: A high-k silicate atomic layer deposition method is disclosed. To produce a hafnium silicate layer, a substrate may be exposed to a pulse of a hafnium precursor, a pulse of an oxidizer, a pulse of a silicon precursor, and a pulse of another oxidizer. A catalyst may additionally be co-flowed with one or more reactants into the chamber through a separate inlet. Alternatively, the catalyst may be flowed to the chamber before the reactant is introduced in a soaking procedure. By either co-flowing the catalyst through separate inlets or by performing a catalyst soak, hafnium silicate formation may proceed at a fast rate and/or at a low temperature.

Abstract: The present invention generally comprises a silicon dioxide atomic layer deposition method. By providing pyridine as a catalyst, water may be utilized as the oxidization source while depositing at a low temperature. Prior to exposing the substrate to the water, the substrate may be exposed to a pyridine soak process. Additionally, the water may be co-flowed to the chamber with the pyridine through separate conduits to reduce interaction prior to entering the chamber. Alternatively, the pyridine may be co-flowed with a silicon precursor that does not react with pyridine.

Abstract: Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate.