Abstract: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

Abstract: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

Abstract: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

Abstract: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

Abstract: A thin film transistor with a channel less than 100 angstroms thick, preferably less than 80 angstroms thick, preferably less than 60 angstroms thick. The very thin channel reduces variability of threshold voltage from one TFT to the next. This is particularly advantageous for TFT memory arrays. It is possible that an extremely thin channel restricts the size of grains, forcing many small grains to be formed.

Abstract: A thin film transistor includes an insulating substrate, an active layer located over the substrate, a gate electrode located over the substrate; and a charge storage region located between the active layer and the gate electrode. The charge storage region includes a tunneling dielectric located adjacent to the active layer, a blocking dielectric located adjacent to the gate electrode and a charge storage dielectric located between the tunneling dielectric and the blocking dielectric. At least one of the tunneling dielectric, the charge storage dielectric and the blocking dielectric comprises a layer having a dielectric constant greater than 3.9, such as a metal oxide layer.

Abstract: Gate dielectric structures for integrated circuits and methods for manufacturing such gate dielectric structures are described. The gate dielectric structures contain gate oxide layers that are provided using a low temperature in-situ steam generation process, thereby providing silicon oxide layers of a very high quality. The gate oxide layers are used primarily in thin film transistors and as the bottom layer in the gate dielectric of silicon-oxide-nitride-oxide-silicon semiconductor devices.

Abstract: A support member for supporting a substrate in a process chamber, the support member having a substrate support surface with one or more isolated recessed areas. A vacuum channel and a gas channel are formed in the support member along a common plane and are coupled to a vacuum source and gas source respectively. The gas channel comprises two or more concentrically disposed annular gas channels encompassing the vacuum channel. The vacuum channel is coupled to the support surface, and in particular to the one or more recessed areas, by a plurality of conduits. A portion of the conduits is disposed diametrically exterior to at least one of the annular gas channels and communicates with the vacuum channel via bypass channels.

Abstract: An alignment mechanism for aligning a substrate on a support member in a process chamber includes a set of guide pins extending from the upper surface of the support member equally spaced about the periphery thereof and spaced to receive a substrate therebetween and align a shadow ring thereover. The inner surfaces of the guide pins are slanted outwardly to form an inverted funnel for receiving and aligning the substrate on the support member. An annular gas groove in the upper surface of the support member provides communication for a supply of purge gas and directs the gas about the peripheral edge of the substrate. The guide pins which extend partially over the gas groove include slots therein that provide fluid communication through the guide pins from the gas groove to the peripheral edge of the substrate.

Abstract: A method for forming a refractory metal layer that features two-stage nucleation prior to bulk deposition of the same. The method includes placing a substrate in a deposition zone, flowing, into the deposition zone during a first deposition stage, a silicon source, such as a silane gas, and a tungsten source, such as tungsten-hexafluoride gas, so as to obtain a predetermined ratio of the two gases therein. During a second deposition stage, subsequent to the first deposition stage, the ratio of the two gases is varied. Specifically, in the first deposition stage there is a greater quantity of silane gas than tungsten-hexafluoride gas. In the second deposition stage there may be a greater quantity of tungsten-hexafluoride than silane.

Abstract: An alignment mechanism for aligning a substrate on a support member in a process chamber includes a set of guide pins extending from the upper surface of the support member equally spaced about the periphery thereof and spaced to receive a substrate therebetween and align a shadow ring thereover. The inner surfaces of the guide pins are slanted outwardly to form an inverted funnel for receiving and aligning the substrate on the support member. An annular gas groove in the upper surface of the support member provides communication for a supply of purge gas and directs the gas about the peripheral edge of the substrate. The guide pins which extend partially over the gas groove include slots therein that provide fluid communication through the guide pins from the gas groove to the peripheral edge of the substrate.

Abstract: An apparatus and process for limiting residue remaining after the etching of metal in a semiconductor manufacturing process, such as etching back a tungsten layer to form tungsten plugs, by passivating the surface of a wafer with a halogen-containing gas are disclosed. The wafer is exposed to the halogen-containing gas in a chamber before a metal layer is deposited on the wafer. The exposure can occur in the same chamber as the metal deposition, or a different chamber. The wafer can remain in the chamber or be moved to another chamber for etching after exposure and deposition.

Abstract: An apparatus and process for limiting residue remaining after the etching of metal in a semiconductor manufacturing process, such as etching back a tungsten layer to form tungsten plugs, by passivating the surface of a wafer with a halogen-containing gas are disclosed. The wafer is exposed to the halogen-containing gas in a chamber before a metal layer is deposited on the wafer. The exposure can occur in the same chamber as the metal deposition, or a different chamber. The wafer can remain in the chamber or be moved to another chamber for etching after exposure and deposition.

Abstract: An apparatus and process for limiting residue remaining after the etching of metal in a semiconductor manufacturing process by injecting a halogen-containing gas without a plasma into a processing chamber. The wafer is then exposed to the remnants of the halogen-containing gas in the chamber before the metal is deposited on the wafer. The exposure can occur in the same chamber as the metal deposition, or a different chamber. The wafer can remain in the chamber or be moved to another chamber for etching after exposure and deposition.