Abstract: An authentication method is used by an automated driving system that includes a vehicle and an external device, the external device communicating with the vehicle to cause the vehicle to implement automated driving. The vehicle holds a first certificate that certifies validity of the vehicle. The external device holds a second certificate that certifies validity of the external device. The authentication method includes: validating a third certificate that certifies validity of a combination of the vehicle and the external device, in accordance with a result of device authentication performed between the vehicle and the external device by reference to the first certificate and the second certificate.

Abstract: An object detection device includes: a camera ECU that measures the bearing of an object by detecting the object from an image captured by a camera and identifying the direction toward the object; a sonar that measures the distance to the object existing around the vehicle; and a position identification unit that identifies the position of the object by combining the measured bearing data and distance data on a grid map that is based on a polar coordinate system and identifying the grid cell where the object exists on the grid map.

Abstract: A memory control apparatus controls access to a DRAM having a plurality of banks. The apparatus comprises a first generating unit configured to generate an access command in accordance with an access request for the DRAM and store the access command in a buffer; a second generating unit configured to generate a bank-designated refresh request for the DRAM; and an issuing unit configured to issue a DRAM command to the DRAM based on an access command stored in the buffer and a refresh request generated by the second generating unit. The second generating unit determines a bank for which the refresh request is generated, based on an access time for each bank of the DRAM by not less than one access command stored in the buffer.

Abstract: A seal chain includes two inner link plates opposed to and spaced apart from each other, a tubular bushing, opposite ends of the bushing being respectively joined to the two inner link plates, a pin rotationally inserted into the bushing, a tubular roller into which the bushing is inserted, the roller being rotationally supported by the bushing, and two outer link plates arranged to externally hold the two inner link plates in between, opposite ends of the pin being respectively joined to the two outer link plates. A recess into which an end of the roller is inserted is formed in an inner surface of each of the inner link plates.

Abstract: In a control circuit, a request storage unit including a plurality of entries for storing an access request, to which a priority and attribute information are applied, stores the received access request, a priority update unit updates the priority of the access request based on the priority and the attribute information of the access request stored in the request storage unit, and a request selection unit selects and transmits the access request stored in the request storage unit based on the updated priority.

Abstract: An aqueous dispersion including a polymer having a 2-oxazoline group; and a surfactant, the surfactant containing a sulfuric acid ester compound represented by the following Chemical Formula (S): R1—O—(R2O)nSO3X??(S) wherein R1 represents an aliphatic hydrocarbon group having 8 to 20 carbon atoms; R2 represents an alkylene group having 2 to 4 carbon atoms; n represents 2 to 15; and X represents a monovalent cation.

Abstract: A memory control apparatus controls access to a DRAM having a plurality of banks. The apparatus comprises a first generating unit configured to generate an access command in accordance with an access request for the DRAM and store the access command in a buffer; a second generating unit configured to generate a bank-designated refresh request for the DRAM; and an issuing unit configured to issue a DRAM command to the DRAM based on an access command stored in the buffer and a refresh request generated by the second generating unit. The second generating unit determines a bank for which the refresh request is generated, based on an access time for each bank of the DRAM by not less than one access command stored in the buffer.

Abstract: The object of the present invention is to provide a (meth)acrylic polymer capable of modifying various thermoplastic resins while suppressing or preventing the degradation of various properties derived from the thermoplastic resins. A copolymer for modifying an acidic proton-containing thermoplastic resin, comprising an oxazoline group-containing monomer unit and a (meth)acrylate unit, wherein a content of the oxazoline group-containing monomer unit is 1 part by mass or more relative to 100 parts by mass of all monomer units.

Abstract: A memory control apparatus controls access to a DRAM having a plurality of banks. The apparatus comprises a first generating unit configured to generate an access command in accordance with an access request for the DRAM and store the access command in a buffer; a second generating unit configured to generate a bank-designated refresh request for the DRAM; and an issuing unit configured to issue a DRAM command to the DRAM based on an access command stored in the buffer and a refresh request generated by the second generating unit. The second generating unit determines a bank for which the refresh request is generated, based on an access time for each bank of the DRAM by not less than one access command stored in the buffer.

Abstract: An authentication method is used by an automated driving system that includes a vehicle and an external device, the external device communicating with the vehicle to cause the vehicle to implement automated driving. The vehicle holds a first certificate that certifies validity of the vehicle. The external device holds a second certificate that certifies validity of the external device. The authentication method includes: validating a third certificate that certifies validity of a combination of the vehicle and the external device, in accordance with a result of device authentication performed between the vehicle and the external device by reference to the first certificate and the second certificate.

Abstract: A seal chain includes two inner link plates opposed to and spaced apart from each other, a tubular bushing, opposite ends of the bushing being respectively joined to the two inner link plates, a pin rotationally inserted into the bushing, a tubular roller into which the bushing is inserted, the roller being rotationally supported by the bushing, and two outer link plates arranged to externally hold the two inner link plates in between, opposite ends of the pin being respectively joined to the two outer link plates. A recess into which an end of the roller is inserted is formed in an inner surface of each of the inner link plates.

Abstract: A memory control apparatus controls access to a DRAM having a plurality of banks. The apparatus comprises a first generating unit configured to generate an access command in accordance with an access request for the DRAM and store the access command in a buffer; a second generating unit configured to generate a bank-designated refresh request for the DRAM; and an issuing unit configured to issue a DRAM command to the DRAM based on an access command stored in the buffer and a refresh request generated by the second generating unit. The second generating unit determines a bank for which the refresh request is generated, based on an access time for each bank of the DRAM by not less than one access command stored in the buffer.

Abstract: Provided is a fraudulent message detection device that detects a fraudulent message in a bus network and includes: a resynchronization detector that detects an edge of a signal on a bus in the bus network and determines whether to perform resynchronization, so as to adjust a sampling point in a one-bit period; a transmission and receiving control unit that obtains a first logical value and a second logical value in a one-bit period after the resynchronization detector determines to perform the resynchronization, the first logical value being a logical value at a sampling point used before the edge is detected, the second logical value being a logical value at a sampling point after the resynchronization is performed; a comparator that compares the first and second logical values; and a fraud detection processing unit that executes post-fraud-detection processing, when the first and second logical values do not coincide.

Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.

Abstract: Provided is a fraudulent message detection device that detects a fraudulent message in a bus network and includes: a resynchronization detector that detects an edge of a signal on a bus in the bus network and determines whether to perform resynchronization, so as to adjust a sampling point in a one-bit period; a transmission and receiving control unit that obtains a first logical value and a second logical value in a one-bit period after the resynchronization detector determines to perform the resynchronization, the first logical value being a logical value at a sampling point used before the edge is detected, the second logical value being a logical value at a sampling point after the resynchronization is performed; a comparator that compares the first and second logical values; and a fraud detection processing unit that executes post-fraud-detection processing, when the first and second logical values do not coincide.

Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

Abstract: One embodiment includes: forming a laminated body by alternately laminating a conducting layer and an interlayer insulating layer on a substrate; forming a memory hole passing through the laminated body; forming a memory gate insulating layer including a charge storage layer on an inner wall of the memory hole; forming a first semiconductor layer on the memory gate insulating layer; forming a cover film on the first semiconductor layer; removing the memory gate insulating layer, the first semiconductor layer, and the cover film on a bottom surface of the memory hole, to expose the substrate; forming an epitaxial layer on the exposed substrate; removing the cover film; and forming the second semiconductor layer along the first semiconductor layer, to electrically couple: the substrate to the first semiconductor layer; and the substrate to the second semiconductor layer, via the epitaxial layer.

Abstract: An optical module-member is provided, including: a layer-shaped optical waveguide; a light-emitting unit substrate including an insulating substrate, light-emitting element-mounting portions where light-emitting elements are configured to be mounted so as to be optically connected to the optical waveguide, and driving element-mounting portions which are electrically connected to the light-emitting element-mounting portions where driving elements for driving the light-emitting elements are configured to be mounted; and a light-receiving unit substrate which is separated from the light-emitting unit substrate, the light-receiving unit substrate including: an insulating substrate, light-receiving element-mounting portions where light-receiving elements are configured to be mounted so as to be optically connected to the optical waveguide, and signal amplification element-mounting portions which are electrically connected to the light-receiving element-mounting portions and where signal amplification elements for

Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.

Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.