Patents by Inventor Makoto Fujiwara

Makoto Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8420293
    Abstract: Embodiments in accordance with the present invention provide waveguide structures and methods of forming such structures where core and laterally adjacent cladding regions are defined. Some embodiments of the present invention provide waveguide structures where core regions are collectively surrounded by laterally adjacent cladding regions and cladding layers and methods of forming such structures.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: April 16, 2013
    Assignees: Sumitomo Bakelite Co., Ltd., Promerus, LLC
    Inventors: Koji Choki, Tetsuya Mori, Ramakrishna Ravikiran, Makoto Fujiwara, Keizo Takahama, Kei Watanabe, Hirotaka Nonaka, Yumiko Otake, Andrew Bell, Larry Rhodes, Dino Amoroso, Mutsuhiro Matsuyama
  • Patent number: 8407488
    Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: March 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Makoto Fujiwara, Yusuke Nemoto, Junichi Yasui, Takuji Maeda, Takayuki Ito, Yasushi Yamada, Shinji Inoue
  • Patent number: 8299988
    Abstract: A pulse signal delay circuit comprises: a first pulse edge delay circuit for generating a first delay timing signal for sequentially outputting a first edge detection delay timing gained by detecting the rising edge of an input pulse signal and delaying the detection timing by a constant delay time a predetermined number of times; a second pulse edge delay circuit for generating a second delay timing signal for sequentially outputting a second edge detection delay timing gained by detecting the falling edge of the input pulse signal and delaying the detection timing by the delay time the number of times; and a delay pulse signal generating circuit for generating and outputting delay pulse signals rising and falling according to the first and second edge detection delay timings, respectively, from the first and second delay timing signals, the first and second edge detection delay timings delayed the same number of times.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: October 30, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Oishi, Makoto Fujiwara
  • Publication number: 20120181148
    Abstract: A conveyor chain constructed so as to prevent a leakage of lubricant oil to the outside. The conveyor chain comprises a plurality of bearing elements operable to revolve in a raceway between an outer circumferential surface of a bush and an inner circumferential surface of a roller. A pair of right and left thrust bearing annular members are press-fitted onto the outer circumferential surface of the bush and are positioned between the inner side surface of an inner link plate and the outwardly-facing end surfaces of the bearing elements. Annular sealing members for sealing lubricant oil within bearing element raceway are disposed between the inner circumferential surface of the roller and an inner circumferential surface of the thrust bearing annular member. The sealing members slidably contact but are not deformed by the inner circumferential surface of the roller.
    Type: Application
    Filed: December 13, 2011
    Publication date: July 19, 2012
    Inventors: Masatsugu Ueno, Makoto Fujiwara
  • Patent number: 8200058
    Abstract: An optical waveguide structure has excellent heat resistance and a low water absorbing property and can be manufactured with a low material cost. Such an optical waveguide structure includes: an optical waveguide having two surfaces, a core layer including core portions and cladding portions each having a refractive index lower than that of each of the core portions, the core layer having two surfaces, and cladding layers provided so as to make contact with the two surfaces of the core layer and having a refractive index lower than that of each of the core portions; and conductor layers provided on the two surfaces of the optical waveguide. In the optical waveguide structure, each of the cladding layers is formed of a norbornene-based polymer as a major component thereof.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: June 12, 2012
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventors: Koji Choki, Tetsuya Mori, Keizo Takahama, Makoto Fujiwara, Kei Watanabe, Hiroshi Owari
  • Patent number: 8190912
    Abstract: An development environment of a high security level is provided for a key-installed system. Development of a program for a system having an LSI device which includes a secure memory is performed by providing another LSI device having the same structure and setting the provided LSI device to a development mode which is different from a product operation mode. Alternatively, the provided LSI device is set to an administrator mode to perform development and encryption of a key-generation program. The LSI device is set to a key-generation mode to execute the encrypted key-generation program, thereby generating various keys.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: May 29, 2012
    Assignee: Panasonic Corporation
    Inventors: Makoto Fujiwara, Yusuke Nemoto, Junichi Yasui, Takuji Maeda, Takayuki Ito, Yasushi Yamada, Shinji Inoue
  • Patent number: 8185746
    Abstract: In a target apparatus which stores at least one piece of domain key information in a first area and a plurality of pieces of content key information each associated with any one of the domain key information in a second area, a method for generating data for detecting tampering of the content key information. The method comprises the steps of encrypting the content key information associated with one of the domain key information using a chain encryption technique, extracting data at predetermined positions in the encrypted content key information, concatenating the pieces of data extracted at the predetermined positions in the encrypted content key information to obtain concatenated data, performing a hash calculation with respect to the concatenated data to obtain a hash value, storing check values corresponding to the data at the predetermined positions in plain text, in the target apparatus, and storing the hash value in the target apparatus.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: May 22, 2012
    Assignee: Panasonic Corporation
    Inventors: Tomoya Satou, Makoto Fujiwara, Kentarou Shiomi, Yusuke Nemoto, Yuishi Torisaki, Kazuya Shimzu, Shinji Inoue, Kazuya Fujimura, Makoto Ochi
  • Publication number: 20120084475
    Abstract: It may be difficult to give bus right to a bus master that cannot output a bus request signal when a bus arbitration apparatus is ready to grant bus permission precisely in a ratio of a preset number of times of the bus acquisition. The bus arbitration apparatus operates to wait until bus request signals of bus masters that have not performed transfers of the preset number of times of the bus acquisition are output while a bus slave operates.
    Type: Application
    Filed: September 15, 2011
    Publication date: April 5, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Makoto Fujiwara
  • Publication number: 20120072681
    Abstract: Memory accesses to a memory device that is in a power saving mode depend on the order of the issuance thereof. Thus, a period of time during which the memory is placed in the power saving mode is sometimes shortened, resulting in less effective power savings. A memory control apparatus, which is connected with a plurality of masters and a plurality of memories having a power saving mode, arbitrates memory accesses from the plurality of the masters, monitors whether each of the plurality of the memories is in the power saving state, and determines the priorities of the memory accesses according to the result of the detection of the power saving mode.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 22, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Makoto Fujiwara, Wataru Ochiai
  • Patent number: 8140727
    Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: March 20, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiaki Minami, Shunichi Kaizu, Yasunari Nagamatsu, Daisuke Shiraishi, Makoto Fujiwara, Koji Moriya, Koichi Morishita
  • Publication number: 20120064458
    Abstract: Embodiments in accordance with the present invention provide waveguide structures and methods of forming such structures where core and laterally adjacent cladding regions are defined. Some embodiments of the present invention provide waveguide structures where core regions are collectively surrounded by laterally adjacent cladding regions and cladding layers and methods of forming such structures.
    Type: Application
    Filed: August 10, 2011
    Publication date: March 15, 2012
    Applicants: PROMERUS, LLC, SUMITOMO BAKELITE COMPANY LIMITED
    Inventors: Koji CHOKI, Tetsuya Mori, Ramakrishna Ravikiran, Makoto Fujiwara, Keizo Takahama, Kei Watanabe, Hirotaka Nonaka, Yumiko Otake, Andrew Bell, Larry Rhodes, Dino Amoroso, Mutsuhiro Matsuyama
  • Patent number: 8134209
    Abstract: Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: March 13, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yagishita, Makoto Fujiwara, Hirohisa Kawasaki, Mariko Takayanagi
  • Patent number: 8122262
    Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: February 21, 2012
    Assignee: Panasonic Corporation
    Inventors: Makoto Fujiwara, Yusuke Nemoto, Junichi Yasui, Takuji Maeda, Takayuki Ito, Yasushi Yamada, Shinji Inoue
  • Publication number: 20120027214
    Abstract: An LSI includes a first decryptor which receives first encrypted key data, and decrypts the first encrypted key data using a first cryptographic key, thereby generating first decrypted key data, a second cryptographic key generator which generates a second cryptographic key based on a second ID, a second encryptor which encrypts the first decrypted key data using the second cryptographic key, thereby generating second encrypted key data, and a second decryptor which decrypts the second encrypted key data using the second cryptographic key, thereby generating second decrypted key data. At a time of key setting, the second encryptor stores the second encrypted key data in a storage unit. At a time of key usage, the second decryptor reads the second encrypted key data from the storage unit.
    Type: Application
    Filed: October 5, 2011
    Publication date: February 2, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Kaoru YOKOTA, Akihito Katsura, Yusuke Nemoto, Yuishi Torisaki, Makoto Fujiwara
  • Publication number: 20110306452
    Abstract: The invention provides a chain transmission mechanism capable of alleviating impact and impact noise caused when a chain engages and contacts with a sprocket, of not increasing the impact and impact noise even if the chain transmission mechanism is driven in heavy load and in high speed, of reducing vibrations, breakage, wear and others of the chain and the sprocket and of improving its durability. Tooth bottoms of the sprocket are formed so as not contact any pin, bush or drive roller of the connector when the chain is wound around the sprocket as guide rollers rotatably supported coaxially with a pin of the chain rolls on a track along the guide rail provided on the side of teeth of the sprocket. The invention provides a guide rail around the sprocket to engage the chain an lit its impact with the sprocket as the mechanism operates.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 15, 2011
    Inventor: Makoto Fujiwara
  • Patent number: 8077867
    Abstract: The present invention relates to a confidential information processing device, a confidential information processing apparatus, and a confidential information processing method, and particularly to a confidential information processing device which performs multiple cryptographic computation for different target data included in a data stream. With this configuration, the context control unit outputs the stream on which the cryptographic computation is performed to an external device or other stream analysis unit. Thus, by setting the number of cryptographic computation on a correspondence table, the number of computation can be set to any number. Thus, the confidential information processing device according to the present invention can perform any number of cryptographic computations on one stream. Furthermore, without outputting the stream whenever a cryptographic computation is completed, multiple cryptographic computations can be performed with one stream input.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: December 13, 2011
    Assignee: Panasonic Corporation
    Inventors: Yusuke Nemoto, Yuishi Torisaki, Makoto Fujiwara, Satoru Kuriki, Masahiro Sano
  • Publication number: 20110294616
    Abstract: There is provided a seal chain in which sealing performance of a seal mechanism is enhanced so as to be able to deal with a displacement radially of the connecting pins, and to be able to keep a sealing function for a long period of time even if highly fluid lubricant is used. Each seal mechanism comprises an inner circumferential ring fitted and fixed onto the end of the bush an annular seal receiving member disposed on the outer peripheral side of the inner circumferential ring so as to be movable in the radial direction and attached with an annular member enclosing a radial seal on the side of the outer link plate, a bellows seal extending between the inner circumferential ring and the annular seal receiving member and deformable in the radial direction and a seal ring provided on the side of the outer link plate facing to the inner link plate at the position corresponding to the annular radial sealing member concentrically with the pin to abut with the annular sealing member to seal the lubricant.
    Type: Application
    Filed: May 12, 2011
    Publication date: December 1, 2011
    Inventor: Makoto Fujiwara
  • Publication number: 20110274424
    Abstract: A lens barrel comprising bayonet type mount projections to detachably attach to a lens-fitting unit of a camera body having a photographic region, wherein mount projections are formed to avoid cross-section of light path area where object light is introduced in the camera body.
    Type: Application
    Filed: July 15, 2011
    Publication date: November 10, 2011
    Applicant: NIKON CORPORATION
    Inventors: Makoto Fujiwara, Yuuichi Katagishi
  • Patent number: 8053166
    Abstract: Embodiments in accordance with the present invention provide waveguide structures and methods of forming such structures where core and laterally adjacent cladding regions are defined. Some embodiments of the present invention provide waveguide structures where core regions are collectively surrounded by laterally adjacent cladding regions and cladding layers and methods of forming such structures.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: November 8, 2011
    Assignees: Sumitomo Bakelite Co. Ltd., Promerus, LLC.
    Inventors: Koji Choki, Tetsuya Mori, Ramakrishna Ravikiran, Makoto Fujiwara, Keizo Takahama, Kei Watanabe, Hirotaka Nonaka, Yumiko Otake, Andrew Bell, Larry Rhodes, Dino Amoroso, Mutsuhiro Matsuyama
  • Publication number: 20110263368
    Abstract: In a seal chain, a seal mechanism comprises a pair of mutually facing seal members, a first seal member of the pair being in contact with an inner plate of the chain, and a second seal member of the pair being in contact with an outer plate of the chain. A pair of resilient annular lips formed on the first seal member are in sliding contact with a surface of the second seal member. Each sealing member has lubricant-filled grooves facing the plate with which it is in contact.
    Type: Application
    Filed: April 4, 2011
    Publication date: October 27, 2011
    Applicant: TSUBAKIMOTO CHAIN CO.
    Inventor: Makoto Fujiwara