Patents by Inventor Makoto Fujiwara

Makoto Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10020364
    Abstract: One embodiment includes: forming a laminated body by alternately laminating a conducting layer and an interlayer insulating layer on a substrate; forming a memory hole passing through the laminated body; forming a memory gate insulating layer including a charge storage layer on an inner wall of the memory hole; forming a first semiconductor layer on the memory gate insulating layer; forming a cover film on the first semiconductor layer; removing the memory gate insulating layer, the first semiconductor layer, and the cover film on a bottom surface of the memory hole, to expose the substrate; forming an epitaxial layer on the exposed substrate; removing the cover film; and forming the second semiconductor layer along the first semiconductor layer, to electrically couple: the substrate to the first semiconductor layer; and the substrate to the second semiconductor layer, via the epitaxial layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Yamasaki, Makoto Fujiwara, Shinji Mori
  • Patent number: 9804345
    Abstract: An optical module-member is provided, including: a layer-shaped optical waveguide; a light-emitting unit substrate including an insulating substrate, light-emitting element-mounting portions where light-emitting elements are configured to be mounted so as to be optically connected to the optical waveguide, and driving element-mounting portions which are electrically connected to the light-emitting element-mounting portions where driving elements for driving the light-emitting elements are configured to be mounted; and a light-receiving unit substrate which is separated from the light-emitting unit substrate, the light-receiving unit substrate including: an insulating substrate, light-receiving element-mounting portions where light-receiving elements are configured to be mounted so as to be optically connected to the optical waveguide, and signal amplification element-mounting portions which are electrically connected to the light-receiving element-mounting portions and where signal amplification elements for
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: October 31, 2017
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventors: Makoto Fujiwara, Shinya Arai
  • Publication number: 20170271527
    Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.
    Type: Application
    Filed: September 29, 2016
    Publication date: September 21, 2017
    Inventors: Masaaki HIGUCHI, Masao SHINGU, Tatsuya KATO, Takeshi MURATA, Makoto FUJIWARA, Masaki KONDO, Muneyuki TSUDA, Takashi KURUSU
  • Patent number: 9754961
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer. The first insulating film has a lower end portion, and a height of the lower end portion of the first insulating film is lower than the height of the upper face of the second semiconductor film.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Yamasaki, Makoto Fujiwara, Daisuke Nishida
  • Publication number: 20170141123
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers; a first semiconductor film including a first portion and a second portion; a first insulating film having a lower surface; and a second semiconductor film having a lower surface. The first portion is provided as one body inside the stacked body. The first portion has a first crystal structure different from a crystal structure of the substrate. The second portion is provided between the first portion and the substrate. The second portion contacts the substrate and has a second crystal structure different from the first crystal structure.
    Type: Application
    Filed: February 29, 2016
    Publication date: May 18, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yosuke MITSUNO, Hiroshi Kanno, Makoto Fujiwara
  • Publication number: 20170077125
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer. The first insulating film has a lower end portion, and a height of the lower end portion of the first insulating film is lower than the height of the upper face of the second semiconductor film.
    Type: Application
    Filed: February 17, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki YAMASAKI, Makoto FUJIWARA, Daisuke NISHIDA
  • Publication number: 20170062451
    Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.
    Type: Application
    Filed: February 17, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masao SHINGU, Katsuyuki SEKINE, Hirokazu ISHIGAKI, Makoto FUJIWARA
  • Patent number: 9566847
    Abstract: A rear opening is provided in the rear part of a vehicle, and a tailgate opens and closes the rear opening. A spoiler is provided at the upper end of the tailgate. Deflectors are provided below the spoiler. The deflectors extend downward along the outer surface of the tail gate from the lower surface of the spoiler and are disposed at positions offset by a predetermined distance from the opposite ends in the vehicle width direction of the spoiler toward a central portion in the vehicle width direction of the spoiler.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: February 14, 2017
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Makoto Fujiwara, Kenichi Hori, Eiji Kimura, Kousuke Katsumata, Yuta Endo
  • Publication number: 20160282571
    Abstract: An optical module-member is provided, including: a layer-shaped optical waveguide; a light-emitting unit substrate including an insulating substrate, light-emitting element-mounting portions where light-emitting elements are configured to be mounted so as to be optically connected to the optical waveguide, and driving element-mounting portions which are electrically connected to the light-emitting element-mounting portions where driving elements for driving the light-emitting elements are configured to be mounted; and a light-receiving unit substrate which is separated from the light-emitting unit substrate, the light-receiving unit substrate including: an insulating substrate, light-receiving element-mounting portions where light-receiving elements are configured to be mounted so as to be optically connected to the optical waveguide, and signal amplification element-mounting portions which are electrically connected to the light-receiving element-mounting portions and where signal amplification elements for
    Type: Application
    Filed: July 1, 2014
    Publication date: September 29, 2016
    Applicant: SUMITOMO BAKELITE CO., LTD.
    Inventors: Makoto FUJIWARA, Shinya ARAI
  • Publication number: 20160272052
    Abstract: A rear opening is provided in the rear part of a vehicle, and a tailgate opens and closes the rear opening. A spoiler is provided at the upper end of the tailgate. Deflectors are provided below the spoiler. The deflectors extend downward along the outer surface of the tail gate from the lower surface of the spoiler and are disposed at positions offset by a predetermined distance from the opposite ends in the vehicle width direction of the spoiler toward a central portion in the vehicle width direction of the spoiler.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 22, 2016
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Makoto Fujiwara, Kenichi Hori, Eiji Kimura, Kousuke Katsumata, Yuta Endo
  • Publication number: 20160268379
    Abstract: One embodiment includes: forming a laminated body by alternately laminating a conducting layer and an interlayer insulating layer on a substrate; forming a memory hole passing through the laminated body; forming a memory gate insulating layer including a charge storage layer on an inner wall of the memory hole; forming a first semiconductor layer on the memory gate insulating layer; forming a cover film on the first semiconductor layer; removing the memory gate insulating layer, the first semiconductor layer, and the cover film on a bottom surface of the memory hole, to expose the substrate; forming an epitaxial layer on the exposed substrate; removing the cover film; and forming the second semiconductor layer along the first semiconductor layer, to electrically couple: the substrate to the first semiconductor layer; and the substrate to the second semiconductor layer, via the epitaxial layer.
    Type: Application
    Filed: September 10, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki YAMASAKI, Makoto FUJIWARA, Shinji MORI
  • Publication number: 20160197094
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction. The second insulating film includes a first film contacting the conductive layers, and a second film provided between each electrode and the first film.
    Type: Application
    Filed: March 17, 2016
    Publication date: July 7, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Makoto FUJIWARA
  • Patent number: 9336163
    Abstract: In a memory control apparatus for issuing a command for a bank corresponding to a transfer request, the transfer request for the corresponding bank is stored. The column address of the transfer request stored at the first is compared with the column addresses of a plurality of subsequent transfer requests. It is determined based on the comparison result whether to issue a command with precharge or a command without precharge for the transfer request stored at the first. The determined command is issued.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 10, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Makoto Fujiwara
  • Patent number: 9324729
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction. The second insulating film includes a first film contacting the conductive layers, and a second film provided between each electrode and the first film.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Higuchi, Katsuyuki Sekine, Makoto Fujiwara
  • Publication number: 20150372002
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction. The second insulating film includes a first film contacting the conductive layers, and a second film provided between each electrode and the first film.
    Type: Application
    Filed: September 11, 2014
    Publication date: December 24, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaaki HIGUCHI, Katsuyuki SEKINE, Makoto FUJIWARA
  • Patent number: 9208356
    Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: December 8, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Makoto Fujiwara, Yusuke Nemoto, Junichi Yasui, Takuji Maeda, Takayuki Ito, Yasushi Yamada, Shinji Inoue
  • Patent number: 9172535
    Abstract: An LSI includes a first decryptor which receives first encrypted key data, and decrypts the first encrypted key data using a first cryptographic key, thereby generating first decrypted key data, a second cryptographic key generator which generates a second cryptographic key based on a second ID, a second encryptor which encrypts the first decrypted key data using the second cryptographic key, thereby generating second encrypted key data, and a second decryptor which decrypts the second encrypted key data using the second cryptographic key, thereby generating second decrypted key data. At a time of key setting, the second encryptor stores the second encrypted key data in a storage unit. At a time of key usage, the second decryptor reads the second encrypted key data from the storage unit.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: October 27, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kaoru Yokota, Akihito Katsura, Yusuke Nemoto, Yuishi Torisaki, Makoto Fujiwara
  • Publication number: 20150301290
    Abstract: The object of the present invention is to provide an optical wiring part which can connect the optical waveguide and another optical element with high optical coupling efficiency while inhibiting the decrease of the transmission loss, and an electronic device with high reliability including the optical wiring part, the present invention provides an optical wiring part including a tape-shaped optical waveguide and a ferrule having a penetration hole which is formed from a base end to a tip end of the ferrule, and a part of the optical waveguide in a longitudinal direction is inserted into the penetration hole, wherein at least one main surface of two main surfaces of the optical waveguide is fixed to an inner wall of the penetration hole, and there is a clearance between the inner wall of the penetration hole and two side surfaces of the optical waveguide.
    Type: Application
    Filed: November 22, 2013
    Publication date: October 22, 2015
    Applicant: SUMITOMO BAKELITE CO., LTD.
    Inventors: Daisuke FUJIWARA, Makoto FUJIWARA, Masaaki KATO
  • Patent number: 9116292
    Abstract: An object of the present invention is to provide an optical waveguide module which has a small optical coupling loss between the light element and the optical waveguide and can perform high-quality optical communication, a method for producing the optical waveguide module with high efficiency, and an electronic apparatus which includes the optical waveguide module and can perform high-quality optical communication, and the present invention provides an optical waveguide module including: an optical waveguide including a core portion, a clad portion that is provided to cover a side surface of the core portion, and an optical path-converting unit that is provided partway along the core portion or on an extended line of the core portion and that converts an optical path of the core portion to the outside of the clad portion; an optical element that is provided over the clad portion; a circuit board that is provided between the optical waveguide and the optical element and has a through-hole formed along an optic
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: August 25, 2015
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventors: Makoto Fujiwara, Motoya Kaneta
  • Patent number: RE45614
    Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: July 14, 2015
    Assignee: Sony Corporation
    Inventors: Masahiro Igarashi, Tetsuo Motomura, Ryuji Kaneko, Makoto Fujiwara, Yoshinori Tanaka, Hiromi Ogata