Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.

Abstract: According to one embodiment, a semiconductor device includes an insulating film, a catalytic layer and a wiring layer. The insulating film has a hole. The catalytic layer is formed at the bottom of the hole, at the peripheral wall of the hole, and on the upper surface of the insulating film outside the hole. A contact is formed of a carbon nanotube provided on the portion of the catalytic layer at the bottom of the hole. The wiring layer is formed of graphene and provided on the catalytic layer outside the hole in contact with the carbon nanotube. The catalytic layer at the bottom of the hole is a perforated film, and the catalytic layer outside the hole is a continuous film.

Abstract: According to one embodiment, a semiconductor device in which CNTs are used for a contact via comprise a substrate including a contact via groove, a catalyst layer for CNT growth which is formed at the bottom of the groove, and a CNT via formed by filling the CNTs into the groove in which the catalyst layer is formed. Each of the CNTs is formed by stacking a plurality of graphene layers in a state in which they are inclined depthwise with respect to the groove, and formed such that ends of the graphene layers are exposed on a sidewall of the CNT. Further, the CNT is doped with at least one element from the sidewall of the CNT.

Abstract: According to one embodiment, a semiconductor device in which CNTs are used for a contact via comprises a substrate includes a contact via groove, a catalyst layer for CNT growth which is formed at the bottom of the groove, and a CNT via formed by filling the CNTs into the groove in which the catalyst layer is formed. Each of the CNTs is formed by stacking a plurality of graphene layers in a state in which they are inclined depthwise with respect to the groove, and formed such that ends of the graphene layers are exposed on a sidewall of the CNT. Further, the CNT is doped with at least one element from the sidewall of the CNT.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.

Abstract: A power-generating module has a base, a power-generating unit that is placed in the base, a plunger that is placed in the base and that vertically reciprocates, and a drive section that interlocks with the reciprocation of the plunger and starts up the power-generating unit. The drive section is biased to a boost-up position where the plunger is boosted up. The drive section has at least two links that turn between the boost-up position and a press-in position where the power-generating unit is started up. Both ends of one of the links are turnably supported by the base. Both ends of another link are turnably supported by the plunger. The links turn in an interlocking manner by coupling to each other.

Abstract: According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another.

Abstract: According to one embodiment, a semiconductor device includes a first wiring, a second wiring disposed in the same layer as the first wiring, a first via connected to a bottom surface of the first wiring and formed of a carbon nanotube, and a second via connected to a bottom surface of the second wiring and formed of a metal.

Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.

Abstract: According to one embodiment, a semiconductor device includes a wiring, a first insulation film, an underlayer deactivation layer, an underlayer, a catalyst layer and a carbon nanotube. The first insulation film is formed on the wiring and includes a hole which exposes the wiring. The underlayer deactivation layer is formed on the first insulation film at a side surface of the hole, and exposes the wiring at a bottom surface of the hole. The underlayer is formed on an exposed surface of the wiring at the bottom surface of the hole and on the underlayer deactivation layer at the side surface of the hole. The catalyst layer is formed on the underlayer at the bottom surface and the side surface of the hole. The carbon nanotube extends from the catalyst layer at the bottom surface of the hole, and fills the hole.

Abstract: According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.

Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.

Abstract: An electric storage device includes at least first to third storage modules and storage-module busbars. The at least first to third storage modules each include a plurality of storage cells. The at least first to third storage modules are arranged next to each other. Storage-module terminals of the at least first to third storage modules are adjacent to each other. The storage-module terminals of the at least first to third storage modules are electrically connected to each other with the storage-module busbars. The storage-module busbars includes a long storage-module busbar and a short storage-module busbar. The long storage-module busbar is provided at a first side of the at least first to third storage modules. The short storage-module busbar is provided at a second side of the at least first to third storage modules. The long storage-module busbar is longer than the short storage-module busbar.

Abstract: A semiconductor device of an embodiment includes: a substrate; a first catalytic metal film on the substrate; graphene on the first catalytic metal film; an interlayer insulating film on the graphene; a contact hole penetrating through the interlayer insulating film; a conductive film at the bottom portion of the contact hole, the conductive film being electrically connected to the graphene; a second catalytic metal film on the conductive film, the second catalytic metal film being subjected to plasma processing with at least one kind of gas selected from hydrogen, nitrogen, ammonia, and rare gas; and carbon nanotubes on the second catalytic metal film.

Abstract: According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer.

Abstract: In relation to fluid pressure devices, a connection apparatus, by which a filter, a regulator and a lubricator that constitute a fluid pressure unit are mutually connected, is equipped with a base member having a hole therein, a pair of first and second fastening members mounted respectively on one side surface and another side surface of the base member, and first and second holders in which the first and second fastening members are retained. Additionally, the first and second holders engage respectively with engagement projections of the filter, the regulator and the lubricator, and first and second nuts are screw-engaged with the first and second fastening members, whereby the fluid pressure devices are connected together through the first and second holders.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.