Patents by Inventor Makoto Wada

Makoto Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160013467
    Abstract: An energy storage module includes an energy storage cell group containing a plurality of energy storage cells stacked in a stacking direction, and a pair of end plates provided at both ends of the energy storage cell group in the stacking direction. A terminal frame is provided at the end plate in order to electrically connect an electrode terminal of the energy storage cell provided at an end in the stacking direction and an output line. The terminal frame is fixed to the end plate by fixing points.
    Type: Application
    Filed: July 10, 2015
    Publication date: January 14, 2016
    Inventors: Masao Kawata, Atsushi Sakurai, Makoto Wada
  • Publication number: 20150325524
    Abstract: According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer.
    Type: Application
    Filed: July 20, 2015
    Publication date: November 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Yuichi YAMAZAKI, Akihiro KAJITA, Atsunobu ISOBAYASHI, Tatsuro SAITO
  • Patent number: 9159615
    Abstract: According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuro Saito, Makoto Wada, Akihiro Kajita, Atsuko Sakata
  • Publication number: 20150255399
    Abstract: A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.
    Type: Application
    Filed: May 20, 2015
    Publication date: September 10, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichi YAMAZAKI, Makoto WADA, Masayuki KITAMURA, Tadashi SAKAI
  • Publication number: 20150253277
    Abstract: A biosensor according to one embodiment includes a first electrode, a second electrode, a third electrode, a first insulation layer, and a carbon nanotube electrode. The first, the second, and the third electrode are formed on a substrate and include a same layer. The first insulation layer is formed on the substrate so as to cover the first, the second, and the third electrode. The first insulation layer includes a first opening formed to expose at least a part of a surface of the first electrode, a second opening formed to expose at least a part of a surface of the second electrode, and a third opening formed to expose at least a part of a surface of the third electrode. The carbon nanotube electrode is formed inside of the first opening. A part of the carbon nanotube protrudes from a surface of the first insulation layer.
    Type: Application
    Filed: July 28, 2014
    Publication date: September 10, 2015
    Inventors: Makoto WADA, Akihiro KAJITA
  • Patent number: 9131611
    Abstract: A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: September 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Makoto Wada, Masayuki Kitamura, Tadashi Sakai
  • Patent number: 9117738
    Abstract: According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: August 25, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Wada, Hisao Miyazaki, Akihiro Kajita, Atsunobu Isobayashi, Tatsuro Saito, Tadashi Sakai
  • Patent number: 9117851
    Abstract: According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: August 25, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Wada, Yuichi Yamazaki, Akihiro Kajita, Atsunobu Isobayashi, Tatsuro Saito
  • Patent number: 9117885
    Abstract: According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: August 25, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuro Saito, Makoto Wada, Akihiro Kajita
  • Patent number: 9117823
    Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: August 25, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Makoto Wada, Tatsuro Saito, Tadashi Sakai
  • Publication number: 20150228538
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, an interlayer insulation film, a plug, a first mark, a second mark, and an upper wiring. The substrate has a device region and a mark formation region. The interlayer insulation film is formed on the substrate. The plug is made of a first metal material in the interlayer insulation film on the device region of the substrate. The first mark is made of the first metal material in the interlayer insulation film on the mark formation region of the substrate. The second mark is made of a second metal material in the interlayer insulation film on the mark formation region of the substrate. The second mark has a concave on a surface thereof. The upper wiring is formed on the interlayer insulation film and is electrically connected to the plug.
    Type: Application
    Filed: July 28, 2014
    Publication date: August 13, 2015
    Inventors: Makoto WADA, Akihiro KAJITA, Atsunobu ISOBAYASHI, Tatsuro SAITO, Taishi ISHIKURA
  • Publication number: 20150206842
    Abstract: According to one embodiment, there is provided a semiconductor device using graphene, includes a catalyst layer formed on or in a substrate along with an interconnect pattern and a graphene layer formed on the catalyst layer. The graphene layer is arranged parallel to a narrower linewidth than the width of the interconnect pattern.
    Type: Application
    Filed: September 5, 2014
    Publication date: July 23, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro SAITO, Makoto WADA, Atsunobu ISOBAYASHI, Akihiro KAJITA, Tadashi SAKAI
  • Publication number: 20150194386
    Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.
    Type: Application
    Filed: March 20, 2015
    Publication date: July 9, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Makoto Wada, Tatsuro Saito, Tadashi Sakai
  • Patent number: 9076795
    Abstract: According to one embodiment, there is provided a semiconductor device using graphene, includes a catalyst layer formed on or in a substrate along with an interconnect pattern and a graphene layer formed on the catalyst layer. The graphene layer is arranged parallel to a narrower linewidth than the width of the interconnect pattern.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: July 7, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro Saito, Makoto Wada, Atsunobu Isobayashi, Akihiro Kajita, Tadashi Sakai
  • Patent number: 9076794
    Abstract: According to one embodiment, a semiconductor device includes a wiring, a first insulation film, an underlayer deactivation layer, an underlayer, a catalyst layer and a carbon nanotube. The first insulation film is formed on the wiring and includes a hole which exposes the wiring. The underlayer deactivation layer is formed on the first insulation film at a side surface of the hole, and exposes the wiring at a bottom surface of the hole. The underlayer is formed on an exposed surface of the wiring at the bottom surface of the hole and on the underlayer deactivation layer at the side surface of the hole. The catalyst layer is formed on the underlayer at the bottom surface and the side surface of the hole. The carbon nanotube extends from the catalyst layer at the bottom surface of the hole, and fills the hole.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: July 7, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro Saito, Makoto Wada, Atsunobu Isobayashi
  • Patent number: 9027970
    Abstract: In relation to fluid pressure devices, a connection apparatus, by which a filter, a regulator and a lubricator that constitute a fluid pressure unit are mutually connected, is equipped with a base member having a hole therein, a pair of first and second fastening members mounted respectively on one side surface and another side surface of the base member, and first and second holders in which the first and second fastening members are retained. Additionally, the first and second holders engage respectively with engagement projections of the filter, the regulator and the lubricator, and first and second nuts are screw-engaged with the first and second fastening members, whereby the fluid pressure devices are connected together through the first and second holders.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: May 12, 2015
    Assignee: SMC Kabushiki Kaisha
    Inventors: Makoto Wada, Koji Katsuta
  • Patent number: 9030012
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: May 12, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Akihiro Kajita, Atsunobu Isobayashi, Tatsuro Saito, Tadashi Sakai, Taishi Ishikura
  • Publication number: 20150123286
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
    Type: Application
    Filed: January 15, 2015
    Publication date: May 7, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Kazuyuki HIGASHI
  • Patent number: 9018696
    Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Kazuyuki Higashi, Naofumi Nakamura, Tsuneo Uenaka
  • Patent number: 9000591
    Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Makoto Wada, Tatsuro Saito, Tadashi Sakai