Patents by Inventor Makoto Wada

Makoto Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140061916
    Abstract: According to one embodiment, a semiconductor device includes an insulating film, a catalytic layer and a wiring layer. The insulating film has a hole. The catalytic layer is formed at the bottom of the hole, at the peripheral wall of the hole, and on the upper surface of the insulating film outside the hole. A contact is formed of a carbon nanotube provided on the portion of the catalytic layer at the bottom of the hole. The wiring layer is formed of graphene and provided on the catalytic layer outside the hole in contact with the carbon nanotube. The catalytic layer at the bottom of the hole is a perforated film, and the catalytic layer outside the hole is a continuous film.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro Saito, Makoto Wada, Atsunobu Isobayashi, Yuichi Yamazaki, Akihiro Kajita
  • Patent number: 8648464
    Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kitamura, Makoto Wada, Yuichi Yamazaki, Masayuki Katagiri, Atsuko Sakata, Akihiro Kajita, Tadashi Sakai, Naoshi Sakuma, Ichiro Mizushima
  • Publication number: 20130249093
    Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.
    Type: Application
    Filed: February 15, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuichi YAMAZAKI, Makoto WADA, Tatsuro SAITO, Tadashi SAKAI
  • Patent number: 8536706
    Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Hayashi, Atsuko Sakata, Kei Watanabe, Noriaki Matsunaga, Shinichi Nakao, Makoto Wada, Hiroshi Toyoda
  • Publication number: 20130217226
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Application
    Filed: September 18, 2012
    Publication date: August 22, 2013
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Makoto WADA, Yuichi YAMAZAKI, Masayuki KATAGIRI, Akihiro KAJITA, Tadashi SAKAI, Naoshi SAKUMA, Ichiro MIZUSHIMA
  • Patent number: 8507138
    Abstract: An ejector for a fuel cell system of the present invention includes a nozzle having a nozzle hole for discharging hydrogen supplied via an inlet port of an ejector body, a diffuser for mixing hydrogen discharged from the nozzle hole and hydrogen off-gas discharged and returned via a circulation passage from a fuel cell, a needle displacing in the axial direction by a driving force of a solenoid, and a bearing member held in a hollow portion of the nozzle, and having a through hole that movably supports the needle in the axial direction.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: August 13, 2013
    Assignee: Keihin Corporation
    Inventors: Kouichi Yamada, Kazunori Fukuma, Makoto Wada
  • Patent number: 8487449
    Abstract: According to one embodiment, a carbon nanotube interconnection includes a first conductive layer, an insulating film, a catalyst underlying film, a catalyst deactivation film, a catalyst film, and carbon nanotubes. An insulating film is formed on the first conductive layer and including a hole. An catalyst underlying film is formed on the first conductive layer on a bottom surface in the hole and on the insulating film on a side surface in the hole. A catalyst deactivation film is formed on the catalyst underlying film on the side surface in the hole. A catalyst film is formed on the catalyst underlying film on the bottom surface in the hole and the catalyst deactivation film on the side surface in the hole. Carbon nanotubes are formed in the hole, the carbon nanotubes including one end in contact with the catalyst film on the bottom surface in the hole.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: July 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Yuichi Yamazaki, Masayuki Katagiri, Masayuki Kitamura, Atsuko Sakata, Akihiro Kajita, Tadashi Sakai, Naohsi Sakuma
  • Patent number: 8482126
    Abstract: According to an embodiment of the present invention, a device includes a substrate, a base body formed on or above the substrate, and a pair of wirings. The base body has a line shape in a plan view and extends along a length direction. The pair of wirings includes first and second catalyst layers formed on both side surfaces of the base body in the length direction of the base body with sandwiching the base body; and first and second graphene layers formed on both side surfaces of the base body in a manner of contacting the first and second catalyst layers, respectively, and extending along the length direction of the base body, the graphene layers includes a plurality of graphenes laminated perpendicularly with respect to both side surfaces of the base body, respectively.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: July 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Yuichi Yamazaki, Akihiro Kajita, Atsuko Sakata
  • Publication number: 20130134592
    Abstract: A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.
    Type: Application
    Filed: November 23, 2012
    Publication date: May 30, 2013
    Inventors: Yuichi YAMAZAKI, Makoto Wada, Masayuki Kitamura, Tadashi Sakai
  • Publication number: 20130093090
    Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.
    Type: Application
    Filed: December 6, 2012
    Publication date: April 18, 2013
    Inventors: Yumi HAYASHI, Atsuko Sakata, Kei Watanabe, Noriaki Matsunaga, Shinichi Nakao, Makoto Wada, Hiroshi Toyoda
  • Patent number: 8423189
    Abstract: A robot system includes a robot arm driven by a motor, a collision detector that detects a collision between the robot arm and an obstacle, which is provided on the robot arm, and a stopping method selector that controls the robot arm by selecting any one of all stopping methods on the basis of the information obtained by the collision detector, thereby selecting a stopping method in accordance with the status of the collision.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Mitsuaki Nakanishi, Makoto Wada
  • Patent number: 8410608
    Abstract: According to one embodiment, a device includes an insulating layer with a first trench, a first interconnect layer in the first trench, the first interconnect layer including copper and includes a concave portion, and a first graphene sheet on an inner surface of the concave portion.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Yuichi Yamazaki
  • Publication number: 20130075929
    Abstract: A semiconductor device of an embodiment includes: a substrate; a first catalytic metal film on the substrate; graphene on the first catalytic metal film; an interlayer insulating film on the graphene; a contact hole penetrating through the interlayer insulating film; a conductive film at the bottom portion of the contact hole, the conductive film being electrically connected to the graphene; a second catalytic metal film on the conductive film, the second catalytic metal film being subjected to plasma processing with at least one kind of gas selected from hydrogen, nitrogen, ammonia, and rare gas; and carbon nanotubes on the second catalytic metal film.
    Type: Application
    Filed: July 5, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Katagiri, Yuichi Yamazaki, Makoto Wada, Tadashi Sakai, Naoshi Sakuma, Mariko Suzuki
  • Publication number: 20130056873
    Abstract: According to an embodiment of the present invention, a device includes a substrate, a base body formed on or above the substrate, and a pair of wirings. The base body has a line shape in a plan view and extends along a length direction. The pair of wirings includes first and second catalyst layers formed on both side surfaces of the base body in the length direction of the base body with sandwiching the base body; and first and second graphene layers formed on both side surfaces of the base body in a manner of contacting the first and second catalyst layers, respectively, and extending along the length direction of the base body, the graphene layers includes a plurality of graphenes laminated perpendicularly with respect to both side surfaces of the base body, respectively.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Wada, Yuichi Yamazaki, Akihiro Kajita, Atsuko Sakata
  • Patent number: 8378335
    Abstract: A semiconductor device according to an embodiment, includes a catalytic metal film, a graphene film, a contact plug, and an adjustment film. The catalytic metal film is formed above a substrate. The graphene film is formed on the catalytic metal film. The contact plug is connected to the graphene film. The adjustment film is formed in a region other than a region connected to the contact plug of a surface of the graphene film to adjust a Dirac point position in a same direction as the region connected to the contact plug with respect to a Fermi level.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Makoto Wada, Tadashi Sakai
  • Patent number: D696097
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: December 24, 2013
    Assignee: SMC Corporation
    Inventors: Makoto Wada, Koji Katsuta
  • Patent number: D696098
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: December 24, 2013
    Assignee: SMC Corporation
    Inventors: Makoto Wada, Koji Katsuta
  • Patent number: D696099
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: December 24, 2013
    Assignee: SMC Corporation
    Inventors: Makoto Wada, Koji Katsuta
  • Patent number: D696100
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: December 24, 2013
    Assignee: SMC Corporation
    Inventors: Makoto Wada, Koji Katsuta
  • Patent number: D696101
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: December 24, 2013
    Assignee: SMC Corporation
    Inventors: Makoto Wada, Koji Katsuta