Abstract: An output terminal of a photoelectric conversion element included in the photoelectric conversion device is connected to a drain terminal and a gate terminal of a MOS transistor which is diode-connected, and a voltage Vout generated at the gate terminal of the MOS transistor is detected in accordance with a current Ip which is generated at the photoelectric conversion element. The voltage Vout generated at the gate terminal of the MOS transistor can be directly detected, so that the range of output can be widened than a method in which an output voltage is converted into a current by connecting a load resistor, and so on.

Abstract: An antenna capable of receiving circularly polarized waves and performing impedance matching between the antenna and an IC (integrated circuit) of a semiconductor device, and a semiconductor device having such an antenna. The antenna has a first conductor pattern with a loop configuration having a cut section, a second conductor pattern, a third conductor pattern, and a feeding section. A first end portion of the second conductor pattern and a first end portion of the third conductor pattern are connected to the first conductor pattern. A second end portion of the second conductor pattern and a second end portion of the third conductor pattern are connected to the feeding section. The total length of the second conductor pattern is longer than the total length of the third conductor pattern, and the second conductor pattern is placed closer to the cut section than the third conductor pattern is.

Abstract: It is an object to provide a display device in which a problem of light leakage from a liquid crystal element in black display is reduced or overcome and the contrast is improved. It is another object to provide a pixel circuit having a function to control a lighting state of a backlight based on each pixel. These objects are achieved by turning off a light-emitting element in display of a black gray scale, and by providing a light-emitting element in each pixel and providing, in a pixel circuit, a function to individually control lighting and non-lighting of the light-emitting element depending on a gray scale to perform display. When a backlight is provided in each pixel, a light-emitting element that is a backlight is turned off when a black gray scale is displayed, whereby reduction in contrast due to light leakage from a liquid crystal element can be prevented.

Abstract: A circuit for stabilizing an electric current includes a constant voltage supplying circuit configured to supply a constant voltage, and a current generating circuit coupled to the constant voltage supplying circuit to generate an electric current based on a predetermined voltage responsive to the constant voltage and to adjust a current amount of the electric current to a predetermined amount by feedback control based on comparison of the predetermined voltage with a voltage appearing across a predetermined resistance responsive to the electric current.

Abstract: The present invention can be applied to a CMOS image sensor in which each pixel circuit of an active pixel sensor array includes a photoelectric conversion element for converting input light into electricity and a switch transistor for controlling the supply of a reset voltage for resetting the photoelectric conversion element to a predetermined voltage, to the photoelectric conversion element. The CMOS image sensor comprises a control circuit for assigning a control signal applied to a control electrode of the switch transistor. The control circuit outputs a first voltage much higher than a supply voltage of the CMOS image sensor so as to make an ON resistance of the switch transistor sufficiently small in the first part of a reset period of the photoelectric conversion element and outputs a second voltage lower than a supply voltage of the CMOS image sensor in the latter part of a reset period of the photoelectric conversion element.

Abstract: A circuit for stabilizing an electric current includes a constant voltage supplying circuit configured to supply a constant voltage, and a current generating circuit coupled to the constant voltage supplying circuit to generate an electric current based on a predetermined voltage responsive to the constant voltage and to adjust a current amount of the electric current to a predetermined amount by feedback control based on comparison of the predetermined voltage with a voltage appearing across a predetermined resistance responsive to the electric current.

Abstract: A CMOS image sensor of the present invention comprises an array of a picture element circuit, a unit of correlated double sampling one picture element line of the array, a charge pump type voltage up unit of supplying a predetermined step-up voltage to the picture element circuit that forms an array and a prevention unit of preventing the noise caused by a pumping operation of the charge pump type voltage up unit. The prevention unit may be a prohibition unit of prohibiting a pumping operation of the charge pump type voltage up unit. In the case where the charge pump type voltage up unit comprises a voltage up circuit for assigning a voltage up output in accordance with an assigned clock and a clock generation circuit for generating a clock in such a way that the voltage up output matches with the predetermined upped voltage, the prohibition unit of prohibiting a pumping operation may comprise a not-assignment unit of not assigning an output of the clock generation unit to the voltage up circuit.

Abstract: A shift register outputs a selection signal for selection of a horizontal sequence of pixels of a two-dimensional pixel array, and includes a vertical shift register for applying a selection signal to the pixel array from either the outer left side or the outer right side of the pixel array, and a voltage applying device for applying a power supply voltage for reading data for a horizontal sequence of pixels from an opposite side of a supply of the selection signal to the pixel array after the selection signal is output.

Abstract: A semiconductor memory device capable of conducting test operations includes a plurality of word drivers which keep word lines in an active state when the word drivers are selected until the word drivers are reset. The semiconductor memory device further includes a control circuit which successively selects more than one of the plurality of word drivers so as to achieve simultaneous activation of word lines corresponding to selected ones of the plurality of word drivers during the test operations.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle-time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A semiconductor integrated circuit includes a plurality of circuits operating in parallel in accordance with a timing signal and having an enabled state and a disabled state, a control circuit setting each of the plurality of circuits to the enable state or the disabled state in accordance with an operation mode, and a timing adjustment circuit which adjusts the timing signal in accordance with a number of circuits which are in the enabled state.

Abstract: A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A semiconductor memory device capable of conducting test operations includes a plurality of word drivers which keep word lines in an active state when the word drivers are selected until the word drivers are reset. The semiconductor memory device further includes a control circuit which successively selects more than one of the plurality of word drivers so as to achieve simultaneous activation of word lines corresponding to selected ones of the plurality of word drivers during the test operations.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A semiconductor circuit has a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and fourth transistors are a first conduction type, and the second and third transistors are a second conduction type opposite to the first conduction type. The semiconductor circuit employs a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a third power supply line for supplying a third voltage outside of the range determined by the first voltage and the second voltage. The first, second, and third transistors are connected in series between the second power supply line and the third power supply line, and the fourth transistor is connected between an input terminal and a control electrode of the first transistor.

Abstract: A semiconductor memory device includes a memory cell array in which a number of sense amplifiers are provided, a plurality of segmented drive lines each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments forming a pair, and a number of trunks for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same.

Abstract: A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.

Abstract: A semiconductor memory having a plurality of banks, a first specify unit, and a second specify unit. The first specify unit is used to specify one of the banks by decoding a bank address signal contained in a row address signal. The second specify unit is used to specify one of the banks by decoding the bank address signal contained in the row address signal, according to bank status signals that indicate whether or not each of the banks is activated. Therefore, the semiconductor memory is used for different bank configurations. Namely, with this arrangement, the semiconductor memory is capable of serving as a memory having a smaller number of banks, to thereby improve convenience.

Abstract: A semiconductor memory device includes a memory cell array in which a number of sense amplifiers are provided, a plurality of segmented drive lines each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments forming a pair, and a number of trunks for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same.