Abstract: A bidirectional switch, having: a first silicon carbide transistor; a first diode which is provided in series with the first silicon carbide transistor, and of which on voltage is lower than that of a built-in diode of the first silicon carbide transistor at a rated current of the bidirectional switch; a second silicon carbide transistor provided in parallel with the first diode; a second diode which is provided in series with the second silicon carbide transistor and in parallel with the first silicon carbide transistor, and of which on voltage is lower than that of a built-in diode of the second silicon carbide transistor at the rated current of the bidirectional switch; and a connection line which connects a first connection point between the first silicon carbide transistor and the first diode, and a second connection point between the second silicon carbide transistor and the second diode, is provided.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a plurality of trenches, a plurality of gate electrodes respectively provided in the trenches, a first conductive film, a first electrode, a second electrode, a plurality of first high-concentration regions, a plurality of second high-concentration regions, and a second conductive film. The first semiconductor region has a first portion and a plurality of second portions respectively at positions facing the plurality of second high-concentration regions in a depth direction. The second conductive film forms a Schottky contact with the plurality of second portions of the first semiconductor region, such that each junction surface between the second conductive film and the first semiconductor region forms a Schottky barrier of a Schottky barrier diode.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate having an active region and a termination region that surrounds the active region in a top view, a first parallel pn layer provided in the semiconductor substrate in the active region, a second parallel pn layer provided in the semiconductor substrate in the termination region, a device structure provided in the active region, a first electrode electrically connected to the device structure, a second electrode, a first semiconductor region selectively provided in the termination region, and a second semiconductor region provided between the second parallel pn layer and the first semiconductor region, and in contact with the first semiconductor region. The second parallel pn layer is provided apart from the first semiconductor region, at a position deeper than the first semiconductor region and closer to an end of the semiconductor substrate than an outer end of the first semiconductor region.

Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.

Abstract: A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.

Abstract: A superjunction silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a parallel pn structure in which epitaxially grown first column regions of the first conductivity type and ion-implanted second column regions of a second conductivity type are disposed to repeatedly alternate with one another, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate electrodes provided in the trenches via gate insulating films, another electrode, and a third semiconductor layer of the first conductivity type. The first column regions have an impurity concentration in a range from 1.1×1016/cm3 to 5.0×1016/cm3.

Abstract: A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.

Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.

Abstract: In an n-type current diffusion region, a first p+-type region underlying a bottom of a trench (gate trench) is provided. In the n-type current diffusion region, a second p+-type region is provided between adjacent trenches, separated from the first p+-type region and in contact with the p-type base region. In the p-type base region, near a side wall of the trench, a third p+-type region is provided a predetermined distance from the side wall of the trench and is separated from the first and the second p+-type regions. The third p+-type region extends in a depth direction, substantially parallel to the side wall of the trench. A drain-side end of the third p+-type region is in contact with the n-type current diffusion region or protrudes a predetermined depth from the interface of the p-type base region and the n-type current diffusion region toward the drain.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.

Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.

Abstract: Plural trenches are provided in a semiconductor substrate. First p+-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p+-type regions disposed in a MOS cell region C? that is substantially half of a region between the adjacent second trenches is in a range of about 2 ?m to 8 ?m.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, first p+-type regions, and a second p+-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p+-type regions are provided with intervals therebetween along a width direction of the trench gate.

Abstract: In mesa regions between adjacent trenches disposed in an n?-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p+-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n+-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p+-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p+-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.

Abstract: Plural trenches are provided in a semiconductor substrate. First p+-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p+-type regions disposed in a MOS cell region C? that is substantially half of a region between the adjacent second trenches is in a range of about 2 ?m to 8 ?m.

Abstract: In an n-type current diffusion region, a first p30-type region underlying a bottom of a trench (gate trench) is provided. In the n-type current diffusion region, a second p30-type region is provided between adjacent trenches, separated from the first p30-type region and in contact with the p-type base region. In the p-type base region, near a side wall of the trench, a third p30-type region is provided a predetermined distance from the side wall of the trench and is separated from the first and the second p30-type regions. The third p30-type region extends in a depth direction, substantially parallel to the side wall of the trench. A drain-side end of the third p30-type region is in contact with the n-type current diffusion region or protrudes a predetermined depth from the interface of the p-type base region and the n-type current diffusion region toward the drain.

Abstract: On a front surface of a semiconductor base, a first n?-type drift region, a second n-type drift region, and a third n+-type drift region are provided. In the front surface of the semiconductor base, a gate trench is provided penetrating the n+-type source region and the p-type base region, and reaching the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region, the p-type base region, and the second and third n-type drift regions, and that reaches the p-type semiconductor region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at the bottom and the corners of the contact trench and forms a Schottky junction with the third n+-type drift region and the second n-type drift region at a side wall of the contact trench.

Abstract: On a front surface of a semiconductor base, a first n?-type drift region and a second n-type drift region are provided. A gate trench is provided that penetrates an n+-type source region and p-type base region, and reaches the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region and the p-type base region, and reaches a p-type semiconductor region, through the second n-type drift region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at a bottom and corners of the contact trench, and forms a Schottky junction with the second n-type drift region at side walls of the contact trench. A depth of the contact trench is a depth by which a mathematical area of a part thereof forming the Schottky junction is a predetermined mathematical area or greater.