Abstract: A MOS type semiconductor device wherein on voltage is low, the rate of rise of current at turn-on time is low, and it is possible to hold down the rate of rise of collector current at turn-on time, and reduce radiation noise. The device includes a stripe-shaped plan-view pattern of protruding semiconductor region on an n-type substrate and having a p-type region sandwiched between an upper side n-type first region and a lower side n-type second region, a top flat portion including a depression region with a depth reaching the p-type region, and an inclined portion between the top flat portion and a bottom flat portion around the protruding semiconductor region; and a gate electrode with one end portion of the gate electrode on a surface within the inclined portion, and another end portion on a surface of the lower side n-type second region in the p-type region side vicinity.

Abstract: A semiconductor device includes semiconductor layers of a first conductivity-type and a second conductivity-type stacked on a silicon carbide semiconductor and having differing impurity concentrations. Trenches disposed penetrating the semiconductor layer of the second conductivity-type form a planar striped pattern; and a gate electrode is disposed therein through a gate insulation film. First and second semiconductor regions respectively of the first and the second conductivity-types have impurity concentrations exceeding that of the semiconductor layer of the second conductivity-type and are selectively disposed therein. The depth of the second semiconductor region exceeds that of the semiconductor layer of the second conductivity-type, but not that of the trenches. The second semiconductor region is arranged at given intervals along the length of the trenches.

Abstract: A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).

Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.

Abstract: In a non-punch-through (NPT) insulated gate bipolar transistor (IGBT), a rear surface structure including a p+ collector layer and a collector electrode is provided on a rear surface of an n? semiconductor substrate and a depletion layer which is spread from a pn junction between a p base region and an n? drift layer when the NPT-IGBT is turned off does not come into contact with the p+ collector layer. A carrier concentration of a region of the n? drift layer that is provided at a depth of 0.3 ?m or less from a pn junction between the n? drift layer and the p+ collector layer is in the range of 30% to 70% of a stored carrier concentration of a region of the n? drift layer that is provided at a depth greater than 0.3 ?m from the pn junction.

Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.

Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.

Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.

Abstract: A MOS type semiconductor device wherein on voltage is low, the rate of rise of current at turn-on time is low, and it is possible to hold down the rate of rise of collector current at turn-on time, and reduce radiation noise. The device includes a stripe-shaped plan-view pattern of protruding semiconductor region on an n-type substrate and having a p-type region sandwiched between an upper side n-type first region and a lower side n-type second region, a top flat portion including a depression region with a depth reaching the p-type region, and an inclined portion between the top flat portion and a bottom flat portion around the protruding semiconductor region; and a gate electrode with one end portion of the gate electrode on a surface within the inclined portion, and another end portion on a surface of the lower side n-type second region in the p-type region side vicinity.

Abstract: A pixel includes a light emitting element and a driving element connected to the light emitting element. After an initial voltage is applied to one end of a current path of the driving element via the signal line, the pixel driving device acquires the threshold voltage of the driving element based on a voltage value at a terminal of the signal line when the initial voltage is cut off and the relaxation time is elapsed. The voltage-current characteristics of the driving element is acquired based on the voltage value at the terminal of the signal line when the current flows into the current path of the driving element via the signal line. The current gain value of the driving element is acquired based on the threshold voltage of the driving element. The image data is corrected based on the acquired threshold voltage.

Abstract: Disclosed is a display apparatus including a plurality of display pixels formed of a plurality of first electrodes provided in one surface side of a substrate, a second electrode which faces each of the first electrodes and display functional layers which are provided between each of the first electrodes and the second electrode and a resistive film having a predetermined resistivity in which one surface side is provided so as to face the other surface side of the second electrode having a predetermined space above the upper surface of a partition wall layer to define a forming region for each of the display pixels and which is disposed so as to be conductive to the other surface side of the second electrode by a pressure applied from outside, and the second electrode constructing the display pixels is double used as an electrode for detecting a position where the pressure is applied.

Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.

Abstract: A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).

Abstract: A display device includes a display panel having a plurality of signal lines and scanning lines with a plurality of display pixels containing current control type light emitting devices; a scan driver circuit which applies a scanning signal to each of the scanning lines and sets the display pixels connected to the scanning lines in a selective state; a signal driver circuit which generates gradation current based on a display data luminosity gradation component and supplies to the display pixels set in the selective state; a precharge circuit which applies a precharge voltage to each signal line and sets a capacity component attached to each of the scanning lines in a predetermined charged state; and an operation control circuit which controls setting of the light emitting devices in a non-light emitting state when the capacity component is set in a predetermined charged state.

Abstract: A data acquisition circuit sets one of the potential value at one end of a signal line and the value of a current flown thereto when one end of a current path of a drive device is connected to a light emitting device with the other end thereof set to a potential value where no current flows to the light emitting device. Then the circuit causes current to flow via the current path and the signal line and acquires one of the value of the current flown to the signal line and the potential value at the one end of the signal line according to the set value. A correction operation circuit acquires a threshold voltage and a current amplification factor of the drive device based on one of the current and potential values thus acquired as well as on one of the potential and current values thus set.

Abstract: A pixel driving device for drive control of pixels, has a image data conversion circuit for generating an original gradation signal by converting an image data, based on a preset conversion property, a signal correction circuit for outputting a corrected gradation signal by adding a correction value acquired based on an electric property parameter of a pixel to the original gradation signal, and a drive signal impressing circuit for impressing a voltage signal corresponding to the corrected gradation signal on one end of a signal line. The original gradation signal has a value that corresponds to a gradation value of the image data and the maximum value of the original gradation signal is set to a value equal to or smaller than a value acquired by subtracting a value corresponding to the correction value from a maximum value in an input range of the drive signal impressing circuit.

Abstract: A light emitting device has a plurality of pixels, each of which includes a drive transistor, a light emitting element and signal lines, a property parameter acquisition circuit which acquires property parameter, a signal correction circuit that generates a corrected gradation signal by correcting the image data based on the property parameter, and a drive signal impressing circuit that impresses a drive signal, generated based on the corrected gradation signal, on the pixel to drive it. The property parameter is constituted of a threshold voltage, a current amplification factor and its irregularity of the drive transistor, and is acquired based on measured voltages of the signal lines after each of a plurality of predetermined settling times elapses from the time when the light emitting device cuts off a voltage subsequent to impressing the voltage on each pixel for a predetermined length of time.

Abstract: A pixel driving device has a voltage impressing circuit that outputs a reference voltage that exceeds a threshold voltage of a drive transistor, a voltage measurement circuit, and a property parameter acquisition circuit that acquires a property parameter related to an electronic property of a pixel. The pixel driving device impresses the reference voltage on the pixel that has a light emitting element and the drive transistor. The voltage measurement circuit acquires voltage of a signal line, as measured voltages, after each of a plurality of the settling times elapsing from the time when the reference voltage is cut. The property parameter acquisition circuit acquires, as property parameters, the threshold voltage and a current amplification factor of drive transistor based on values of a plurality of measured voltages acquired by the voltage measurement circuit.

Abstract: A pixel driving device in which, after a reference voltage exceeds a threshold voltage of a drive transistor is impressed through the signal lines on each pixel equipping a light emitting element and the drive transistor, set the signal lines in a state of high impedance, and acquires a voltage value of one end of the signal lines subsequent to a predetermined settling time elapsing, and acquires the threshold voltage of the drive transistor for each pixel and the current amplification factor of the pixel drive circuit as a first property parameter based on acquired voltage values at the time a plurality of first settling times longer than a predetermined value and acquires an irregularity parameter indicating the irregularity in the current amplification factor based on the value of the first property parameter and the measured voltage value acquired at the time shorter than the predetermined value.

Abstract: A semiconductor device according to the invention includes n-type semiconductor substrate 1; trenches 15 formed in the surface portion of semiconductor substrate 1; a protruding semiconductor region between trenches 15; p-type base layer 2 in the protruding semiconductor region, p-type base layer 2 being positioned as deep as or shallower than trench 15; an n++-type emitter region or a source region in the surface portion of p-type base layer 2; gate insulator film 4a on the first side wall of the protruding semiconductor region; and gate electrode 6 on gate insulator film 4a. Trench 15 is from 0.5 ?m to 3.0 ?m deep and the short side of trench 15 is 1.0 ?m or longer. The short side of the protruding semiconductor region is from 0.5 ?m to 3.0 ?m long. Gate electrode 6 contains electrically conductive polycrystalline silicon as its main component. Gate electrode 6 is from 0.2 ?m to 1.0 ?m thick.