Patents by Inventor Manabu Takei
Manabu Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120184083Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate. Then, on the wafer, a trench to become a scribing line is formed with a crystal face exposed so as to form a side wall of the trench. On that side wall, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to dice a collector electrode, formed on the p collector region, together with the p collector region.Type: ApplicationFiled: January 18, 2012Publication date: July 19, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kazuo SHIMOYAMA, Manabu TAKEI, Haruo NAKAZAWA
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Publication number: 20120086076Abstract: Provision of a super-junction semiconductor device capable of reducing rises in transient on-resistance at the time of repeated switching operation. A super-junction structure is provided that has a striped parallel surface pattern, where a super-junction stripe and a MOS cell 6 stripe are parallel, and a p column Y2 over which no MOS cell 6 stripe is arranged and a p column Y1 over which the MOS cell 6 stripe is arranged are connected at an end.Type: ApplicationFiled: July 13, 2010Publication date: April 12, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventor: Manabu Takei
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Patent number: 8138542Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.Type: GrantFiled: April 21, 2009Date of Patent: March 20, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Koh Yoshikawa, Akio Sugi, Kouta Takahashi, Manabu Takei, Haruo Nakazawa, Noriyuki Iwamuro
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Patent number: 8119496Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: GrantFiled: May 24, 2010Date of Patent: February 21, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Kazuo Shimoyama, Manabu Takei, Haruo Nakazawa
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Publication number: 20110175886Abstract: A display element drive circuit includes a first circuit which holds as a voltage component electric charges based on a gradation signal corresponding to display data, a second circuit which supplies the gradation signal to the electric charge holding circuit at a timing of application of a selection signal, current control type display elements, and a third circuit which generates a driving current based on the voltage component held in the first circuit and supplies the generated driving current to the display element. One of the second and third circuits includes at least one field effect transistor. The field effect transistor includes gate, source and drain electrodes, and a source-side parasitic capacitance formed between the gate and source electrodes and a drain-side parasitic capacitance formed between the gate and drain electrodes of the field effect transistor have different capacitance values.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Applicant: CASIO COMPUTER CO., LTD.Inventors: Ikuhiro YAMAGUCHI, Manabu Takei
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Publication number: 20110115761Abstract: A display device includes a display panel having a plurality of signal lines and scanning lines with a plurality of display pixels containing current control type light emitting devices; a scan driver circuit which applies a scanning signal to each of the scanning lines and sets the display pixels connected to the scanning lines in a selective state; a signal driver circuit which generates gradation current based on a display data luminosity gradation component and supplies to the display pixels set in the selective state; a precharge circuit which applies a precharge voltage to each signal line and sets a capacity component attached to each of the scanning lines in a predetermined charged state; and an operation control circuit which controls setting of the light emitting devices in a non-light emitting state when the capacity component is set in a predetermined charged state.Type: ApplicationFiled: January 20, 2011Publication date: May 19, 2011Applicant: CASIO COMPUTER CO., LTD.Inventors: Manabu TAKEI, Tomoyuki Shirasaki, Ikuhiro Yamaguchi, Tsuyoshi Ozaki, Jun Ogura
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Patent number: 7928932Abstract: A display element drive circuit includes a first circuit which holds as a voltage component electric charges based on a gradation signal corresponding to display data, a second circuit which supplies the gradation signal to the electric charge holding circuit at a timing of application of a selection signal, current control type display elements, and a third circuit which generates a driving current based on the voltage component held in the first circuit and supplies the generated driving current to the display element. One of the second and third circuits includes at least one field effect transistor. The field effect transistor includes gate, source and drain electrodes, and a source-side parasitic capacitance formed between the gate and source electrodes and a drain-side parasitic capacitance formed between the gate and drain electrodes of the field effect transistor have different capacitance values.Type: GrantFiled: September 26, 2005Date of Patent: April 19, 2011Assignee: Casio Computer Co., Ltd.Inventors: Ikuhiro Yamaguchi, Manabu Takei
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Publication number: 20110081752Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: ApplicationFiled: May 24, 2010Publication date: April 7, 2011Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventors: Kazuo SHIMOYAMA, Manabu TAKEI, Haruo NAKAZAWA
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Patent number: 7898507Abstract: A display device which displays image information based on display data comprising a display panel having a plurality of signal lines and scanning lines with a plurality of display pixels containing current control type light emitting devices; a scan driver circuit applies a scanning signal to each of the scanning lines and sets the display pixels connected to the scanning lines in a selective state; a signal driver circuit generates gradation current based on the display data luminosity gradation component and supplies to the display pixels set in the selective state; a precharge circuit applies a precharge voltage to each signal line and sets a capacity component attached to each of the scanning lines in a predetermined charged state; and an operation control circuit controls setting of the light emitting devices in a non-light emitting state when the capacity component is set in a predetermined charged state.Type: GrantFiled: June 16, 2005Date of Patent: March 1, 2011Assignee: Casio Computer Co., Ltd.Inventors: Manabu Takei, Tomoyuki Shirasaki, Ikuhiro Yamaguchi, Tsuyoshi Ozaki, Jun Ogura
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Patent number: 7863151Abstract: A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.Type: GrantFiled: June 23, 2009Date of Patent: January 4, 2011Assignee: Fuji Electric Systems Co., Ltd.Inventor: Manabu Takei
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Patent number: 7855699Abstract: A display device includes a display panel having rows of scanning lines and columns of data lines; and a matrix of display pixels near intersections of the scanning lines and the data line. A scanning driver circuit which selects display pixels of rows connected to some of the scanning lines, and a signal driver generates display data for each display pixel. The display panel has scanning line groups which constitute sets of scanning lines through which simultaneous selection is performed by the scanning driver circuit; a plurality of scanning signal lines connected to each of the scanning line groups; and a plurality of data line groups which constitute sets of the data lines corresponding to a line count of the display pixels of the rows connected to each of the scanning line groups within the data lines.Type: GrantFiled: August 18, 2005Date of Patent: December 21, 2010Assignee: Casio Computer Co., Ltd.Inventors: Tomoyuki Shirasaki, Manabu Takei
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Publication number: 20100264455Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: ApplicationFiled: June 28, 2010Publication date: October 21, 2010Applicant: FUJI ELECTRIC HOLDINGS CO. LTDInventors: Haruo NAKAZAWA, Kazuo SHIMOYAMA, Manabu TAKEI
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Publication number: 20100245308Abstract: Disclosed is a display apparatus including a plurality of display pixels formed of a plurality of first electrodes provided in one surface side of a substrate, a second electrode which faces each of the first electrodes and display functional layers which are provided between each of the first electrodes and the second electrode and a resistive film having a predetermined resistivity in which one surface side is provided so as to face the other surface side of the second electrode having a predetermined space above the upper surface of a partition wall layer to define a forming region for each of the display pixels and which is disposed so as to be conductive to the other surface side of the second electrode by a pressure applied from outside, and the second electrode constructing the display pixels is double used as an electrode for detecting a position where the pressure is applied.Type: ApplicationFiled: March 29, 2010Publication date: September 30, 2010Applicant: Casio Computer Co., Ltd.Inventor: Manabu TAKEI
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Publication number: 20100245343Abstract: A pixel includes a light emitting element and a driving element connected to the light emitting element. After an initial voltage is applied to one end of a current path of the driving element via the signal line, the pixel driving device acquires the threshold voltage of the driving element based on a voltage value at a terminal of the signal line when the initial voltage is cut off and the relaxation time is elapsed. The voltage-current characteristics of the driving element is acquired based on the voltage value at the terminal of the signal line when the current flows into the current path of the driving element via the signal line. The current gain value of the driving element is acquired based on the threshold voltage of the driving element. The image data is corrected based on the acquired threshold voltage.Type: ApplicationFiled: March 30, 2010Publication date: September 30, 2010Applicant: CASIO COMPUTER CO., LTD.Inventors: Manabu TAKEI, Jun Ogura, Shunji Kashiyama, Tsuyoshi Ozaki
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Patent number: 7795621Abstract: A thin film transistor panel including: a transparent substrate; scanning lines made of a light blocking electroconductive material to be formed on the transparent substrate; data lines formed on the transparent substrate to be perpendicular to the scanning lines and made of a light blocking electroconductive material; thin film transistors, each provided with a transparent gate electrode connected to one of the scanning lines, a transparent drain electrode connected to one of the data lines, a transparent source electrode and a transparent semiconductor thin film; and transparent pixel electrodes connected to the thin film transistors, wherein each of the pixel electrodes is formed to cover at least a part of the gate electrode of each of the thin film transistors.Type: GrantFiled: February 16, 2006Date of Patent: September 14, 2010Assignee: Casio Computer Co., Ltd.Inventors: Ikuhiro Yamaguchi, Manabu Takei, Motohiko Yoshida
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Patent number: 7791568Abstract: A display panel (110) includes a plurality of optical elements (OEL) each having a pair of electrodes and performing an optical operation according to current passing between the pair of electrodes, a current line (DL), a switch circuit (Tr2) that passes a write current (Ia) with a predetermined current value through the current line (DL) during a selection time (Tse) and stops passing current during a non-selection time (Tnse), and a current storage circuit (Tr1, Tr3, Cs, Cp) that stores current data according to the current value of the write current (Ia) passing through the current line (DL) during the selection time (Tse) and that supplies a drive current (Ib) having a current value, which is obtained by subtracting a predetermined offset current (Ioff) from the current value of the stored write current (Ia), to the optical elements (OEL) during the non-selection time (Tnse).Type: GrantFiled: February 21, 2008Date of Patent: September 7, 2010Assignee: Casio Computer Co., Ltd.Inventors: Hiroyasu Yamada, Manabu Takei
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Patent number: 7790519Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.Type: GrantFiled: May 29, 2007Date of Patent: September 7, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Setsuko Wakimoto, Manabu Takei, Shinji Fujikake
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Patent number: 7776672Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: GrantFiled: March 27, 2006Date of Patent: August 17, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
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Patent number: 7741192Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: GrantFiled: August 19, 2005Date of Patent: June 22, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Kazuo Shimoyama, Manabu Takei, Haruo Nakazawa
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Publication number: 20100140657Abstract: A semiconductor device according to the invention includes n-type semiconductor substrate 1; trenches 15 formed in the surface portion of semiconductor substrate 1; a protruding semiconductor region between trenches 15; p-type base layer 2 in the protruding semiconductor region, p-type base layer 2 being positioned as deep as or shallower than trench 15; an n++-type emitter region or a source region in the surface portion of p-type base layer 2; gate insulator film 4a on the first side wall of the protruding semiconductor region; and gate electrode 6 on gate insulator film 4a. Trench 15 is from 0.5 ?m to 3.0 ?m deep and the short side of trench 15 is 1.0 ?m or longer. The short side of the protruding semiconductor region is from 0.5 ?m to 3.0 ?m long. Gate electrode 6 contains electrically conductive polycrystalline silicon as its main component. Gate electrode 6 is from 0.2 ?m to 1.0 ?m thick.Type: ApplicationFiled: November 12, 2009Publication date: June 10, 2010Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventor: Manabu TAKEI