Patents by Inventor Marco Maccarrone
Marco Maccarrone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9984756Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: August 31, 2017Date of Patent: May 29, 2018Assignee: Micron Technology, Inc.Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20170365345Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: August 31, 2017Publication date: December 21, 2017Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 9779821Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: April 24, 2017Date of Patent: October 3, 2017Assignee: Micron Technology, Inc.Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20170229183Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 9632730Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: March 7, 2016Date of Patent: April 25, 2017Assignee: Micron Technology, Inc.Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20160188259Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 9281064Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: February 26, 2015Date of Patent: March 8, 2016Assignee: Micron Technology, Inc.Inventors: Marco Maccarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20150170745Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: February 26, 2015Publication date: June 18, 2015Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 8982627Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: November 11, 2013Date of Patent: March 17, 2015Assignee: Micron Technology, Inc.Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 8700978Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.Type: GrantFiled: February 25, 2013Date of Patent: April 15, 2014Assignee: Micron Technology, Inc.Inventors: Guido Lomazzi, Ilaria Motta, Marco Maccarrone
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Publication number: 20140071767Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: November 11, 2013Publication date: March 13, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Marco MacCarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 8582364Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: June 7, 2011Date of Patent: November 12, 2013Assignee: Micron Technology, Inc.Inventors: Marco Maccarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20130242652Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.Type: ApplicationFiled: February 25, 2013Publication date: September 19, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Marco Maccarrone, Guido Lomazzi, Ilaria Motta
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Patent number: 8386895Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.Type: GrantFiled: May 19, 2010Date of Patent: February 26, 2013Assignee: Micron Technology, Inc.Inventors: Marco Maccarrone, Guido Lomazzi, Ilaria Motta
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Publication number: 20110289376Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.Type: ApplicationFiled: May 19, 2010Publication date: November 24, 2011Inventors: Marco Maccarrone, Guido Lomazzi, Ilaria Motta
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Publication number: 20110235411Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: June 7, 2011Publication date: September 29, 2011Inventors: Marco Maccarrone, Giuseppe Giannini, Demetrio Pellicone
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Patent number: 8018771Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: GrantFiled: May 19, 2008Date of Patent: September 13, 2011Inventors: Marco Maccarrone, Giuseppe Giannini, Demetrio Pellicone
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Publication number: 20100039858Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.Type: ApplicationFiled: May 19, 2008Publication date: February 18, 2010Applicant: STMicroelectronics S.r.l.Inventors: Marco MACCARRONE, Giuseppe GIANNINI, Demetrio PELLICONE
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Patent number: 6507183Abstract: Presented is an analog voltage value measuring device for measuring any of a set of voltage references that are generated inside a memory architecture. The selected voltage to be measured is connected to a facility line through a multiplexer. The memory architecture includes a set of output buffers connected to a respective set of output pads. The device also includes a converter block, connected between the facility line and the output buffers of the memory architecture for converting a measured analog value of a voltage reference selected by the multiplexer to a digital value, which is presented on the output pads. A method of measuring an analog voltage value in a memory device is also disclosed. The method includes selecting an analog voltage value from the set of voltage values; transferring the selected analog value onto the facility line; converting the selected analog value to a digital value; and presenting the digital value on the output pads.Type: GrantFiled: June 29, 2000Date of Patent: January 14, 2003Assignee: STMicroelectronics S.r.l.Inventors: Jacopo Mulatti, Marco Maccarrone
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Patent number: 6392936Abstract: Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference.Type: GrantFiled: June 30, 2000Date of Patent: May 21, 2002Assignee: STMicroelectronics S.r.l.Inventors: Jacopo Mulatti, Marco Maccarrone