Abstract: A circuit device for measuring the threshold voltage distribution among electrically programmable, non-volatile memory cells, which device comprises a differential amplifier having a first input connected to a first circuit leg including at least one memory cell and a second input connected to a second or reference circuit leg, and circuit means effective to cause an unbalance in the values of the currents flowing in the reference leg. The device is connected between a first supply voltage reference and a second voltage reference, and said circuit means comprise a generator of a varying current as a function of the supply voltage which is associated with the reference leg.

Abstract: An end-of-count detecting device for nonvolatile memories, comprising a decoder in the form of a wired OR structure of a number of transistors of the same type, the gate terminals of which are fed with a count signal generated by a counter element and having a predetermined end-of-count value to be detected. A load, which may be static, pseudo-dynamic or dynamic, is provided between the common node of the decoder transistors and a reference potential line; and the decoder output formed by the common node assumes a different logic level according to whether or not the end-of-count value coded by the wired OR structure is reached. A number of wired OR structures may be arranged side by side with an array of transistors for detecting a number of end-of-count values of the same counter element.

Abstract: A read circuit comprises at least one array branch connected to at least one bit line, and a reference branch connected to a reference line. The array and reference branches each comprise a precharge circuit and load interposed between the supply and the bit line and reference line respectively. The reference load is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line. The reference line is connected to an extra-current transistor which is only turned on during equalization so that, during equalization, the selected bit line is supplied with a high current approximating that supplied to the reference line. As such, if the cell to be read is written, the output voltage of the array branch is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.

Abstract: An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits, each one associated with a respective memory matrix portion or group of columns, and a plurality of programming load control circuits, each one controlling the activation of one respective programming load circuit according to the logic state of a respective data line carrying a datum to be programmed; the memory device comprises a group of redundancy bit lines and an associated redundancy programming load circuit; each programming load control circuit comprises decoding means supplied with signals which, when a defective column address is supplied to the memory device during programming, are generated from a matrix portion identifying code stored in a non-volatile register wherein the defective column address is stored, and switch means responsive to a decoded signal at the output of said decoding means to enable the activation of the redundancy programming load

Abstract: A current source including a current mirror circuit and an active load circuit which form a reference branch, for setting a reference current value, and a mirroring branch, defining an output current value, connected between supply and ground. A voltage stabilizing transistor is interposed between the current mirror circuit and the load circuit in the reference branch only, and is so biased as to maintain its gate terminal at a predetermined voltage. As such, the potential with respect to ground of the drain terminal of the reference branch load transistor is fixed, so that its drain-source voltage drop (and the current through it) is substantially independent of supply voltage. The current source may be used to advantage in an oscillator for generating the: clock signal of a nonvolatile memory.

Abstract: In a nonvolatile memory comprising a data amplifying unit and an output element mutually connected by a connection line, the noise suppressing circuit comprises a network for generating a noise suppressing signal which is synchronized substantially perfectly with a signal controlling data loading from the amplifying unit to the output unit, presents a very short duration, equal to the switching time of the output unit, and freezes the amplifying unit during switching of the output unit to prevent this from altering the data stored in the amplifying unit or internal circuits of the memory. The same signal also blocks an address amplifying unit on the address bus.

Abstract: A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.

Abstract: A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage being powered between a first and a second voltage reference and having a first input terminal connected to a resistive divider of the first reference voltage and an output terminal fed back to said input through a current mirror, and a source-follower transistor controlled by the output and connected to the cells through a programming line. Also provided is a MOS transistor which connects to ground the programming line and a corresponding resistive path connected between the current mirror and the second voltage reference.

Abstract: A load timing circuit including an output simulation circuit similar to the output circuits of the memory, so as to present the same propagation delay; a simulating signal source for generating a data simulating signal; a synchronizing network for detecting a predetermined switching edge of the data simulating signal and enabling supply of the signal to the output simulation circuit and data supply to the output circuits of the memory; a combinatorial network for detecting propagation of the data simulating signal to the output of the output simulation circuit and disabling the data simulating signal; and a reset element for resetting the timing circuit.

Abstract: A memory line decoding driver is so biased that the P channel pull-up transistor biasing the final inverter conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage alternatively connects the gate terminal of the pull-up transistor to a capacitor, with which the charge is distributed, and to the supply.

Abstract: An integrated circuit for checking the utilization rate of redundancy memory elements in semiconductor memory device, comprising a matrix of memory elements and a redundancy circuitry which comprises a plurality of programmable non-volatile memory registers, each supplied with address signals to generate a redundancy selection signal for the selection of an associated redundancy memory element when the address signals coincide with the address stored therein, and combinatorial circuit means supplying the non-volatile memory registers with an inhibition signal for inhibiting the generation of the respective redundancy selection signals when the address signals coincide with the address stored in a non-programmed non-volatile memory register; the integrated circuitry comprises multiplexing circuit means, controlled by a control signal generated by a control circuitry of the memory device, for transmitting the redundancy selection signals to output pads of the memory device when the control signal is activated;