Abstract: A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.

Abstract: An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.

Abstract: An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.

Abstract: An electronic circuit generates a stable voltage signal for the polarization during a reading step of a UPROM redundancy cell incorporating at least one memory element of EPROM or Flash type, having at least one terminal to be polarized, and MOS transistors which connect such memory element to a low voltage power supply reference. The circuit includes a current mirror structure with a first control branch and a second output branch. The current mirror stricture includes a first series of MOS transistors (M2, M3, M4) in said first branch between the supply reference and a ground; and a second series of transistors (M5, M6, M7) in said second branch. The circuit also includes an input terminal connected to the gate terminal of a transistor of the first series of transistors and an output terminal corresponding to an interconnection node of the second series of transistors. The stable voltage is obtained through a current which passes through at least a pair of transistors of the second series.

Abstract: A driving circuit supplied by a supply voltage and a reference voltage, generates an output signal and comprises a first circuit adapted to selectively couple the output signal to the reference voltage or to an internal voltage line internal to the driving circuit in response to a first control signal. The driving circuit also includes a switching circuit adapted to selectively couple the internal voltage line to the supply voltage. A boosting circuit is connected to the internal voltage line and is adapted to bring the internal voltage line to a boosted voltage. The switching circuit and the boosting circuit are controlled by a second control signal to be alternatively activatable, in such a way to bring the internal voltage line either to the supply voltage or to the boosted voltage.

Abstract: A circuit for providing a first reading phase after a Power-On-Reset in a memory device. The circuit includes a comparator, a reference generator that generates a reference voltage signal that is supplied to one input of the comparator, and a voltage divider that generates an output signal that is supplied to another input of the comparator. The reference voltage signal reaches its steady operational value before the supply voltage, and the output signal has the same linear pattern as the supply voltage with a different angular coefficient. The comparator outputs a control signal for starting the first reading phase of the memory device. In one preferred embodiment, the memory device has a single power supply and a zero consumption standby mode. Additionally, there is provided a method for providing a first reading phase after a Power-On-Reset in a memory device.

Abstract: A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.

Abstract: Switching circuit that receives a supply voltage, a reference voltage, a line adapted to carry a negative voltage and a control signal, the switching circuit capable of providing at an output a voltage alternatively equal to the reference voltage or to the voltage of the line in response to the control signal. The circuit includes a first MOSFET with a first electrode operationally connected to the line, a second electrode operationally connected to the output, and a control electrode, a second MOSFET with a first electrode operationally connected to the reference voltage, a second electrode operationally connected to the output, and a control electrode, and driving circuitry adapted to bring the control electrodes of the first and second MOSFETs respectively to the supply voltage and to the voltage of the line or, alternatively, to the voltage of the line and to the supply voltage, in response to the control signal.

Abstract: A band-gap reference voltage generator comprises an operational amplifier comprising a first input and a second input, the first input being coupled to a first feedback network and the second input being coupled to a second feedback network both coupled to an output of the operational amplifier providing a reference voltage. The first feedback network contains an emitter-base junction of first bipolar junction transistor and the second feedback network contains an emitter-base junction of second bipolar junction transistor. A selectively activated current supply supplies a bias current to the operational amplifier, the current supply being deactivatable in a substantially zero power consumption operating condition for turning the reference voltage generator off. A start-up circuit activated upon start-up of the reference voltage generator for a fixed, prescribed time interval forces a start-up current to flow through the first bipolar junction transistor means.

Abstract: The present invention relates to an electronic power on reset circuit of the type including a comparator having at least two inputs and one output for receiving a first reference signal from a generator block and a second signal proportional to a supply voltage from a divider block and for producing an output initialization signal. Advantageously the output is connected to a third turn off enablement input of the comparator through the series of an inverter pair. The generator block and the divider block also include respective turn off enablement inputs connected downstream of the inverter pair.

Abstract: The read circuit presents a current mirror circuit including a first and second load transistor interposed between the supply line and a respective first and second output node. The first output node is connected to a cell to be read, the second output node is connected to a generating stage generating a reference current having a predetermined characteristic, and the size of the second load transistor is N times greater than the first load transistor. To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit presents a current balancing branch connected between the first output node and ground for generating an equalizing current presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.

Abstract: A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.

Abstract: The present invention is directed to a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type having a control terminal and a conduction terminal to be biased, a register with inverters connected to the memory element, and MOS transistors connecting the memory element with a reference low voltage power supply. There is provided a precharge network for the conduction terminal of the flash cell and the network incorporates a complementary pair of transistors. The second transistor of the pair is a natural N-channel MOS type. With the UPROM cell is associated a circuit portion for generating a second live output signal to be applied to the control terminal of the second transistor. The circuit portion includes a timing section and a generation section for the second live output signal.

Abstract: The current flowing through a cell to be read, forming part of a nonvolatile memory array and presenting a characteristic with a predetermined slope, is amplified N times and compared with a reference current presenting a two portion characteristic: a first portion extending between a predetermined threshold value and a trigger value, and presenting a slope equal to that of the memory cell characteristic, and a second portion extending from the trigger value, and presenting a slope amplified N times with respect to that of the cell characteristic and therefore equal to the amplified slope of the cell.

Abstract: A circuit architecture for testing a programmable logic matrix, e.g., the PLA type, has a group of input latches and a corresponding group of output latches connected to the matrix, and test information paths structured with at least one data bus and one address bus. The input latch and the output latch are connected electrically to the test data bus and to the test address bus to allow matrix testing with considerable time saving over known circuitry.

Abstract: An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default state until it is programmed with an address of one of the defective memory cells. A control circuit generates a test signal during an identification mode. A detect circuit is coupled to the control circuit and to the redundancy address register and generates a default-detect signal in response to the test signal when the redundancy address register contains the default state. A data-bus multiplexer that is coupled to the redundancy-cell selection circuit, the data bus, and the control circuit couples the default detect signal to the data bus in response to the test signal.

Abstract: A count unit for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter and a number of registers equal in number to the count functions involved. The registers store the preceding count value and, when their content is to be incremented or in any way altered, load it into the counter which provides for performing the required operation, at the end of which, the content of the counter is stored in the respective register. One of the registers presents a second parallel input for externally loading an initial data which may be transferred to the other registers via the counter.

Abstract: A method for programming non-volatile row redundancy memory registers. Each register is associated with a respective pair of redundancy row and each one programmable to store in two subsets of a set of memory cells a pair of addresses of a respective pair of adjacent defective rows. Each memory register is supplied with row address signals and with a respective selection signal belonging to a set of column address signals.

Abstract: A charge pump circuit including a number of pull-up stages connected in parallel with one another between a reference potential line and an output line. Each stage includes a capacitor having a first terminal connected to a charging and discharging node, and a second terminal connected to a pull-up node for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node is connected to the supply line via a charging transistor having a control terminal connected to a high-voltage bias node formed by the adjacent stage in the opposite operating phase, for charging the capacitor substantially up to the supply voltage.

Abstract: A method for testing an electrically programmable non-volatile memory including a cell matrix and an internal state machine which governs the succession and timing of the memory programming phases includes excluding the internal state machine, modifying at least one of the control signals to program the cell matrix, and verifying programming correctness.