Abstract: A semiconductor memory device designed to mitigate degradation due to heat, and methods of forming such a device, are described. In one example, a memory cell in a memory device includes an insulating layer formed over a substrate, a horizontal crossbar electrode formed over the insulating layer, a metal oxide resistive memory layer formed over the horizontal crossbar electrode, and a vertical crossbar electrode formed over the resistive switching memory layer. In one aspect of the embodiments, the horizontal crossbar electrode includes a thermally conductive horizontal crossbar layer formed over the insulating layer and a platinum horizontal crossbar electrode formed over the thermally conductive horizontal crossbar layer. The thermally conductive horizontal crossbar layer can be a layer of copper for thermal dissipation of heat away from the memory cell during set and reset operations, reducing degradation in the memory device.

Abstract: A vertical interconnect via having a first array of first metal interconnect wires extending along a first lateral direction made from a first material and a second array of second interconnect wires extending along a second lateral direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a metal-insulator-metal structure. The said metal-insulator-metal structure transforms to metal-metal-metal structure upon an application of electric pulse.

Abstract: A resistive floating electrode device (RFED) provides a logic cell or non-volatile storage or dynamic or static random access memory on an extremely compact matrix with individual cells scalable to the minimum available lithographic feature size regime by providing atomic switches connected in anti-parallel relationship, preferably with a common inert electrode. Programming is facilitated by limiting current to a compliance current level in order to maintain an OB state from which the cell can be written to either the 0 or 1 state. A perfecting feature of the invention provides for selective operation of a cell as a diode or in a volatile or non-volatile storage mode within the same memory array. A series connection of three or more RFEDs in accordance with the invention having different ON state currents, OFF state currents and reset currents can be used as adaptive, neural or chaotic logic cells.

Abstract: A memory device having a first array of first electrodes extending along a first direction made from a first material and a second array of second electrodes extending along a second direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a two-terminal resistive memory cell, said memory cell formed by a conductive path between said first and second electrodes.

Abstract: Multiple patterned exposures of a single layer of image reversal resist prior to and following image reversal processing, upon development, respond to the respective exposures as either a positive or a negative resist, allowing a desired shape of a resist structure to be built up from any of a number of combinations of primitive masks. Exploiting the image reversal resist in this manner allows several types of diffraction distortion to be entirely avoided and for many sophisticated lithographic processes to he reduced in complexity by one-half or more while any desired resist structure shape can be formed form a limited number of primitive mask patterns. A regimen, which may be automated as an executable algorithm for a computer may be followed to evaluate different combinations of masks which are valid to produce a desired resist structure shape and select the optimum mask pattern combination to do so.

Abstract: A resistive floating electrode device (RFED) provides a logic cell or non-volatile storage or dynamic or static random access memory on an extremely compact matrix with individual cells scalable to the minimum available lithographic feature size regime by providing atomic switches connected in anti-parallel relationship, preferably with a common inert electrode. Programming is facilitated by limiting current to a compliance current level in order to maintain an OB state from which the cell can be written to either the 0 or 1 state. A perfecting feature of the invention provides for selective operation of a cell as a diode or in a volatile or non-volatile storage mode within the same memory array. A series connection of three or more RFEDs in accordance with the invention having different ON state currents, OFF state currents and reset currents can be used as adaptive, neural or chaotic logic cells.

Abstract: A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.

Abstract: Multiple patterned exposures of a single layer of image reversal resist prior to and following image reversal processing, upon development, respond to the respective exposures as either a positive or a negative resist, allowing a desired shape of a resist structure to be built up from any of a number of combinations of primitive masks. Exploiting the image reversal resist in this manner allows several types of diffraction distortion to be entirely avoided and for many sophisticated lithographic processes to he reduced in complexity by one-half or more while any desired resist structure shape can be formed form a limited number of primitive mask patterns. A regimen, which may be automated as an executable algorithm for a computer may be followed to evaluate different combinations of masks which are valid to produce a desired resist structure shape and select the optimum mask pattern combination to do so.

Abstract: A method of manufacturing a non-volatile memory device, including providing at least one control gate layer on a substrate. A passage may be created between the at least one control gate layer and the substrate. In the passage at least one filling layer may be provided. A floating gate structure including the filling layer may be formed, as well as a control gate structure including the at least one control gate layer, the control gate structure being in a stacked configuration with the floating gate structure.

Abstract: An intermediate product in the manufacture of a vertical multiple-channel FET device containing alternating —Si—[(SiGe)—Si]u- stacked layers is shown, as well as a process for selectively etching the SiGe layers in such a stacked layer system, and products obtained from such selective etching. Differential Ge content is added to the successive layers to provide uniform removal of the sacrificial SiGe layers.

Abstract: Providing a first layer of a semiconductor structure having at least one air gap between conductive lines formed in the first layer. The air gap extends into the first layer from a first surface of the first layer. A barrier dielectric material over the first surface and the air gap is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap. An air gap can extend from a first surface of the first layer to at least a portion of side surfaces of the at least two conductive lines to expose at least a portion of the side surfaces.

Abstract: A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.

Abstract: An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterized in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.

Abstract: Providing a first layer of a semiconductor structure having at least one air gap between conductive lines formed in the first layer. The air gap extends into the first layer from a first surface of the first layer. A barrier dielectric material over the first surface and the air gap is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap. An air gap can extend from a first surface of the first layer to at least a portion of side surfaces of the at least two conductive lines to expose at least a portion of the side surfaces.

Abstract: A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises providing a semiconductor substrate, providing a first layer of a first semiconductor material over the semiconductor substrate, and providing a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. The method further comprises removing a portion of the first layer and a portion of the second layer selectively according to the different rates of removal so as to provide a lateral layer and the vertical channel portion of the inverted T shaped channel structure and removing a portion of the lateral layer so as to provide the horizontal channel portion of the inverted T shaped channel structure.

Abstract: A method of sealing an air gap in a layer of a semiconductor structure comprises providing a first layer of the semiconductor structure having at least one air gap for providing isolation between at least two conductive lines formed in the first layer. The at least one air gap extends into the first layer from a first surface of the first layer. The method further comprises forming a barrier layer of a barrier dielectric material over the first surface of the first layer and the at least one air gap. The barrier dielectric material is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap.

Abstract: A method of sealing an air gap in a layer of a semiconductor structure comprises providing a first layer of the semiconductor structure having at least one air gap for providing isolation between at least two conductive lines formed in the first layer. The at least one air gap extends into the first layer from a first surface of the first layer. The method further comprises forming a barrier layer of a barrier dielectric material over the first surface of the first layer and the at least one air gap. The barrier dielectric material is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap.

Abstract: An intermediate product in the manufacture of a vertical multiple-channel FET device containing alternating —Si—[(SiGe)—Si]u- stacked layers is shown, as well as a process for selectively etching the SiGe layers in such a stacked layer system, and products obtained from such selective etching. Differential Ge content is added to the successive layers to provide uniform removal of the sacrificial SiGe layers.

Abstract: An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterised in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.

Abstract: A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises providing a semiconductor substrate, providing a first layer of a first semiconductor material over the semiconductor substrate and providing a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. The method further comprises removing a portion of the first layer and a portion of the second layer selectively according to the different rates of removal so as to provide a lateral layer and the vertical channel portion of the inverted T shaped channel structure and removing a portion of the lateral layer so as to provide the horizontal channel portion of the inverted T shaped channel structure.