Abstract: A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.

Abstract: A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.

Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Abstract: A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.

Abstract: A method of forming isolation trenches in a semiconductor fabrication process to reduce transistor channel edge effect currents includes forming a masking structure overlying a substrate to expose a first area of the substrate. Spacers are formed on sidewalls of the masking structure. The spacers cover a perimeter region of the first area thereby leaving a second smaller area exposed. The region underlying the second area is etched to form an isolation trench that is then filled with a dielectric. The spacers are removed to expose the perimeter region. Using the masking structure and the trench dielectric as a mask, an impurity distribution is implanted into a portion of the substrate underlying the perimeter region. The impurity distribution thus surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate. The perimeter impurity distribution dopant, in a typical case, is p-type for NMOS transistors and n-type for PMOS.

Abstract: A method for forming a dielectric layer is disclosed herein. In accordance with the method, a first material is provided (303) which comprises a suspension of nanoparticles in a liquid medium. A dielectric layer is then formed (305) on the substrate from the suspension through an evaporative process.

Abstract: A semiconductor fabrication process includes forming a recess in a semiconductor substrate. A silicon germanium film is formed on a sidewall of the recess. A gate dielectric and gate electrode are formed adjacent the silicon germanium film. Source/drain regions are then formed wherein a first source/drain region is adjacent a first side of the gate electrode in an upper surface of the substrate and a second source/drain region adjacent a second side of the gate electrode is below a lower surface of the recess. Etching the exposed portion of the substrate may be done so as to form a rounded corner at the junction of the recess sidewall and the recess lower surface. The silicon germanium film formation is preferably epitaxial. An epitaxial silicon film may be formed adjacent the silicon germanium film.

Abstract: A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics (16) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer (18), quantum confinement of carriers within conductive layer (18) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device (10) can be reduced. Additional conductive layers (e.g. 28) may be used to provide more carriers.

Abstract: A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.

Abstract: A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axial stress are both compressive for P-channel transistors and both tensile for N-channel transistors. The result is that carrier mobility is enhanced for both short channel and long channel transistors. Both transistor types can be included on the same integrated circuit.

Abstract: A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being <100>. In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.

Abstract: A method of forming a semiconductor device includes forming a first layer over a semiconductor substrate and forming a second layer over the first layer. The second layer includes silicon and has an etch selectivity to the second layer that is greater than approximately 1,000. In one embodiment, the second layer is a porous material, such as porous silicon, porous silicon germanium, porous silicon carbide, and porous silicon carbon alloy. A gate insulator is formed over the second layer and a control electrode is formed over the gate insulator. The first layer is selectively removed with respect to the second layer and the semiconductor substrate.

Abstract: Silicon carbon is used as a diffusion barrier to germanium so that a silicon layer can be subsequently formed without being contaminated with germanium. This is useful in separating silicon layers from silicon germanium layers in situations in which both silicon and silicon germanium are desired to be present on the same semiconductor device such as for providing different materials for optimizing carrier mobility between N and P channel transistors and for a raised source/drain of silicon in the case of a silicon germanium body.

Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

Abstract: A method for forming a semiconductor device (10) includes providing a substrate (20) having a surface; forming an insulating layer (22) over the surface of the substrate (20); forming a first patterned conductive layer (30) over the-insulating layer (22); forming a second patterned conductive layer (32) over the first patterned conductive layer (30); forming a patterned non-insulating layer (34) over the second patterned conductive layer (32); and selectively removing portions of the first and second patterned conductive layers (30, 32) to form a notched control electrode for the semiconductor device (10).

Abstract: A semiconductor on insulator transistor is formed beginning with a bulk silicon substrate. An active region is defined in the substrate and an oxygen-rich silicon layer that is monocrystalline is formed on a top surface of the active region. On this oxygen-rich silicon layer is grown an epitaxial layer of silicon. After formation of the epitaxial layer of silicon, the oxygen-rich silicon layer is converted to silicon oxide while at least a portion of the epitaxial layer of silicon remains as monocrystalline silicon. This is achieved by applying high temperature water vapor to the epitaxial layer. The result is a silicon on insulator structure useful for making a transistor in which the gate dielectric is on the remaining monocrystalline silicon, the gate is on the gate dielectric, and the channel is in the remaining monocrystalline silicon under the gate.

Abstract: A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.

Abstract: A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies.

Abstract: A method for forming a semiconductor device having isolation structures decreases leakage current. A channel isolation structure decreases leakage current through a channel structure. In addition, current electrode dielectric insulation structures are formed under current electrode regions to prevent leakage between the current electrodes.

Abstract: A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.