Abstract: Techniques for forming gate dielectric layers (702) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions (604, 606) are formed prior to formation of structures included in the gate structure (804) of the semiconductor device, where the gate structures (804) are preferably formed using low temperature operations that allow the amorphous silicon regions (604, 606) to remain in an amorphous state. Source/drain regions (1004, 1006) are formed in the amorphous silicon regions (604, 606), and then the substrate is annealed to recrystallize the amorphous regions.

Abstract: A split-gate EEPROM transistor includes a channel region (22) formed in a vertically disposed semiconductor body (58) and residing intermediate to a drain region (26) and a source region (24). A select gate electrode (28) is horizontally disposed on a semiconductor substrate (20). A floating gate electrode (30) resides adjacent to the channel region (22) and overlies the select gate electrode (28). A control gate electrode (32) resides adjacent to the control gate electrode (30) and also overlies the select gate electrode (28). In operation, the select gate electrode (28) regulates the flow of electrical charge from the source region (24) into the channel region (22), and provides a field plate electrical isolation for adjacent memory cells in an EEPROM array.

Abstract: Techniques for forming gate dielectric layers (702) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions (604, 606) are formed prior to formation of structures included in the gate structure (804) of the semiconductor device, where the gate structures (804) are preferably formed using low temperature operations that allow the amorphous silicon regions (604, 606) to remain in an amorphous state. Source/drain regions (1004, 1006) are formed in the amorphous silicon regions (604, 606), and then the substrate is annealed to recrystallize the amorphous regions.

Abstract: The present invention relates to a method to locate particles of a predetermined species within a solid, more specifically to form an oxy-nitride dielectric for VLSI applications. A layer (18) of a substance (YZ) is formed upon a solid (10) and a chemical reaction is performed between the substance (YZ) and a gas (X), thereby releasing particles (Z) of a predetermined species which incorporate into the solid (10). This method is used, for example, to form an oxy-nitride dielectric by incorporating nitrogen within a silicon oxide layer (28′).

Abstract: A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).

Abstract: A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) and a portion of the insulating layer (11) exposed by the opening (22). A thin-film gate electrode (20) is positioned in the opening (22) and defines a thin-film channel region (24) in the thin-film channel layer (16). The thin-film gate electrode (20) is separated from the thin-film channel region (24) by a gate dielectric layer (18). The thin-film channel region (24) extends along vertical wall surfaces (26, 28) of the thin-film source and drain regions (12, 14) providing an extended channel length for the thin-film transistor.

Abstract: Insulated gate semiconductor device (10) and a method of manufacturing the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) includes an N-channel transistor (15) and a P-channel transistor (16). The N-channel transistor (15) has a gate electrode (35) that has a central portion (28) and two adjacent gate extensions (49, 52). Likewise the P-channel transistor (16) has a gate electrode (35') which has a central portion (29) and two adjacent gate extensions (53, 54). The gate extensions (49, 52, 53, 54) allow the formation of graded channel regions underneath the gate electrodes (35, 35') and adjacent to the source (57, 59) and drain (58, 62) regions by offsetting an LDD or a single heavily doped source/drain implant from channel regions which are covered by the gate extensions (49, 52 53, 54).

Abstract: A monolithic semiconductor body (26) resides in an opening (16) formed in an insulating layer (14). The monolithic semiconductor body (26) includes an elongated region (20) filling the opening (16) in the insulating layer (14) and contacting a semiconductor region (12). The monolithic semiconductor body (26) further includes a surface region (24) overlying the elongated region (20) and a portion of the surface (22) of the insulating layer (14) adjacent to the opening (16). The monolithic semiconductor body (26) is fabricated by first depositing a layer of semiconductor material into the opening (16), then planarizing the surface of the insulating layer (14). Next, a selective deposition process is carried out to form the surface region (24) using the semiconductor material in the opening (16) as a nucleation site. The radius of curvature of the surface region (24) is determined by the amount of controlled overgrowth during the selective deposition process.

Abstract: Insulated gate semiconductor device (10) and a method of manufacturing the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) includes an N-channel transistor (55) and a P-channel transistor (60). The N-channel transistor (55) has a gate electrode (22') that has a central portion (22) and gate electrode extensions (41) adjacent to the central portion (22). Likewise the P-channel transistor (60) has a gate electrode (24') that has a central portion (24) and gate electrode extensions (42) adjacent to the central portion (24). The gate electrode extensions (41, 42) are formed by filling openings (34, 36) with a gate electrode material. The openings are used for the formation of graded channel regions underneath the gate electrode extensions (41, 42).

Abstract: An insulated gate field effect transistor having a vertically layered elevated source/drain structure includes an electrically conductive suppression region for resistance to hot carrier injection. The device includes a semiconductor substrate of first conductivity type having a gate insulator disposed on the surface of that substrate. A gate electrode, in turn, is disposed on the gate insulator. A lightly doped drain region of second conductivity type is formed in the substrate in alignment with the gate electrode. An electrically conductive suppression region having a first low electrical conductivity is positioned to electrically contact the drain region, but is electrically isolated from the gate electrode and is spaced a first distance from the gate electrode. A heavily doped drain contact also contacts the drain region and is spaced further away from the gate electrode than is the electrically conducted suppression region.