Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a fin having a stack of nanowire-like channel regions. The stack includes at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region. The FET includes source and drain electrodes on opposite sides of the fin. The FET also includes a dielectric separation region including SiGe between the first and second nanowire-like channel regions extending completely from a surface of the second channel region facing the first channel region to a surface of the first channel region facing the second channel region. The FET includes a gate stack extending along a pair of sidewalls of the stack. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions.

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.

Abstract: A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial epitaxial gate stressor is deposited on the fin, causing strain in the fin. SD structures are then formed to anchor the ends of the fin, and the sacrificial epitaxial gate stressor is removed.

Abstract: A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet field effect transistor may be composed of a III-V semiconductor material, and the gate, which may be separated from the channel by a high dielectric constant dielectric layer, may also be composed of a III-V semiconductor material. Adjusting the composition of the gate may result in a change in the affinity of the gate, in turn resulting in a change in the threshold voltage. In some embodiments the channel is composed, for example, of InxGa1-xAs, with x between 0.23 and 0.53, and the gate is composed of InAs1-yNy with y between 0.0 and 0.4, and the values of x and y may be adjusted to adjust the threshold voltage.

Abstract: Multi-layer fin field effect transistor devices and methods of forming the same are provided. The devices may include a fin shaped channel structure on a substrate. The channel structure may include stressor layers stacked on the substrate and a channel layer between the stressor layers, and the stressor layers may include a semiconductor material having a wide bandgap that is sufficient to confine carriers to the channel layer and having a lattice constant different from a lattice constant of the channel layer to induce stress in the channel layer. The devices may also include source/drain regions on respective first opposing sides of the channel structure and a gate on second opposing sides of the channel structure and between the source/drain regions.

Abstract: Methods of forming a layer of silicon germanium include forming an epitaxial layer of Si1-xGex on a silicon substrate, wherein the epitaxial layer of Si1-xGex has a thickness that is less than a critical thickness, hc, at which threading dislocations form in Si1-xGex on silicon; etching the epitaxial layer of Si1-xGex to form Si1-xGex pillars that define a trench in the epitaxial layer of Si1-xGex, wherein the trench has a height and a width, wherein the trench has an aspect ratio of height to width of at least 1.5; and epitaxially growing a suspended layer of Si1-xGex from upper portions of the Si1-xGex pillars, wherein the suspended layer defines an air gap in the trench beneath the suspended layer of Si1-xGex.

Abstract: A method of forming a horizontal nanosheet device or a horizontal nanowire device includes forming a dummy gate and a series of external spacers on a stack including an alternating arrangement of sacrificial layers and channel layers, deep etching portions of the stack between the external spacers to form electrode recesses for a source electrode and a drain electrode, performing an etch-back on portions of the sacrificial layers to form internal spacer recesses above and below each of the channel layers, forming doped internal spacers in the internal spacer recesses, and forming doped extension regions of the source electrode and the drain electrode by outdiffusion of dopants from the doped internal spacers. The method may also include epitaxially regrowing the source electrode and the drain electrode in the electrode recesses.

Abstract: A method of forming a horizontal nanosheet device or a horizontal nanowire device includes forming a dummy gate and a series of external spacers on a stack including an alternating arrangement of sacrificial layers and channel layers, deep etching portions of the stack between the external spacers to form electrode recesses for a source electrode and a drain electrode, performing an etch-back on portions of the sacrificial layers to form internal spacer recesses above and below each of the channel layers, forming doped internal spacers in the internal spacer recesses, and forming doped extension regions of the source electrode and the drain electrode by outdiffusion of dopants from the doped internal spacers. The method may also include epitaxially regrowing the source electrode and the drain electrode in the electrode recesses.

Abstract: A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.

Abstract: According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum VDD includes: determining an x value in InxGa1?xAs according to the BTBT leakage and the maximum VDD, and forming a channel utilizing InxGa1?xA, wherein x is not 0.53.

Abstract: A method for forming a low parasitic capacitance contact to a source-drain structure of a fin field effect transistor device. In some embodiments the method includes etching a long trench down to the source-drain structure, the trench being sufficiently long to extend across all the of source-drain regions of the device. A conductive layer is formed on the source-drain structure, and the trench is filled with a first fill material. A second, narrower trench is opened along a portion of the length of the first trench, and filled with a second fill material. The first fill material may be conductive, and may form the contact. If the first fill material is not conductive, a third trench may be opened, in the portion of the first trench not filled with the second fill material, and filled with a conductive material, to form the contact.

Abstract: Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel.

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.

Abstract: A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

Abstract: FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side.

Abstract: Exemplary embodiments provide for fabricating a biaxially strained nanosheet.

Abstract: Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O3 post treatment. Aspects of the exemplary embodiments include: forming a semiconductor body upon a substrate; cleaning the surface of the semiconductor body; depositing a first dielectric layer on the semiconductor body; performing an O3 treatment to form a new interface layer that incorporates material from the substrate and material from the first dielectric layer; and performing gate stack processing, including deposition of a gate electrode.

Abstract: A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures.